IP Library Granted Patent US 8,154,111
Granted Patent B2
US 8,154,111 · App. 10/662,248 · Granted Apr 10, 2012

Near chip size semiconductor package

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,154,111
App. No.
10/662,248
Granted
Apr 10, 2012
Kind
B2
Abstract

A semiconductor package that can fit semiconductor chips of various sizes without having to change the footprint of the carrier package. One aspect of the semiconductor package comprises a leadframe, a semiconductor chip attached to the leadframe, electrical connectors electrically connecting the semiconductor chip to the leadframe, and a sealing material. The leadframe has a plurality of leads, with each one of the plurality of leads having an upper side, a lower exposed side, and a laterally exposed side. The upper side of each one of the plurality of leads defines a generally co-planar surface. Further, after sealing material encapsulates the components of the semiconductor package in a spatial relationship, the lower exposed side and the lateral exposed side of the plurality of leads are exposed to the outside surface of the semiconductor package.

Claims (40)

1. A semiconductor package, comprising:

a leadframe comprising a plurality of leads segregated into two sets, the leads of each set being linearly aligned and arranged in spaced, generally parallel relation to each other such that each of the leads of one set extends in opposed relation to a respective one of the leads of the remaining set, each of the leads defining opposed, generally planar top and bottom sides;

a semiconductor chip partially overlapping and attached to the top side of at least one of the leads of each of the sets, the semiconductor chip being electrically connected to at least one of the leads; and

a sealing material at least partially encapsulating the leadframe and the semiconductor chip such that the bottom side of each of the leads is exposed within the sealing material.

2. The semiconductor package of claim 1 wherein:

each of the leads further defines an inner end and a notched surface which is disposed in opposed relation to the bottom side and extends to the inner end;

each of the leads has a first thickness between the top and bottom sides which exceeds a second thickness between the bottom side and the notched surface; and

the semiconductor chip partially overlaps and is attached to the notched surface of at least one of the leads of each of the sets.

3. The semiconductor package of claim 2 wherein the semiconductor chip is electrically connected to the top side of at least one of the leads via a conductive wire which is covered by the sealing material.

4. The semiconductor package of claim 2 wherein the semiconductor chip is electrically connected to the notched surface of at least one of the leads via a solder ball which is covered by the sealing material.

5. The semiconductor package of claim 2 wherein the notched surfaces of the leads extend in generally co-planar relation to each other.

6. The semiconductor package of claim 1 wherein:

each of the leads further defines an inner end and a notched surface which is disposed in opposed relation to the top side and extends to the inner end; and

each of the leads has a first thickness between the top and bottom sides which exceeds a second thickness between the top side and the notched surface.

7. The semiconductor package of claim 6 wherein the semiconductor chip is electrically connected to the top side of at least one of the leads via a conductive wire which is covered by the sealing material.

8. The semiconductor package of claim 1 wherein:

each of the leads further defines an outer end; and

the sealing material encapsulates the leadframe such that the outer end of each of the leads is exposed within the sealing material.

9. The semiconductor package of claim 1 wherein the bottom sides of the leads extend in generally co-planar relation to each other.

10. The semiconductor package of claim 1 wherein the top sides of the leads extend in generally co-planar relation to each other.

11. A leadframe comprising:

a peripheral tie bar; and

a plurality of leads connected to the tie bar and segregated into two sets, the leads of each set being linearly aligned and arranged in spaced, generally parallel relation to each other such that each of the leads of one set extends in opposed relation to a respective one of the leads of the remaining set, each of the leads defining:

opposed, generally planar top and bottom sides;

an inner end; and

a notched surface which is disposed in opposed relation to the bottom side and extends to the inner end;

each of the leads having a first thickness between the top and bottom sides which exceeds a second thickness between the bottom side and the notched surface.

12. The leadframe of claim 11 wherein the notched surfaces of the leads extend in generally co-planar relation to each other.

13. The leadframe of claim 11 wherein the bottom sides of the leads extend in generally co-planar relation to each other.

14. The leadframe of claim 11 wherein the top sides of the leads extend in generally co-planar relation to each other.

15. A leadframe comprising:

a peripheral tie bar; and

a plurality of leads connected to the tie bar and segregated into two sets, the leads of each set being linearly aligned and arranged in spaced, generally parallel relation to each other such that each of the leads of one set extends in opposed relation to a respective one of the leads of the remaining set, each of the leads defining:

opposed, generally planar top and bottom sides;

an inner end; and

a notched surface which is disposed in opposed relation to the top side and extends to the inner end;

each of the leads having a first thickness between the top and bottom sides which exceeds a second thickness between the bottom side and the notched surface.

16. The leadframe of claim 15 wherein the notched surfaces of the leads extend in generally co-planar relation to each other.

17. The leadframe of claim 15 wherein the bottom sides of the leads extend in generally co-planar relation to each other.

18. The leadframe of claim 15 wherein the top sides of the leads extend in generally co-planar relation to each other.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2020
From: AMKOR TECHNOLOGY, INC.
To: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE.LTD.
Reel/Frame 054067/0135 →
SECURITY INTEREST Recorded Aug 1, 2018
From: AMKOR TECHNOLOGY, INC.
To: BANK OF AMERICA, N.A., AS AGENT
Reel/Frame 046683/0139 →
PATENT SECURITY AGREEMENT Recorded Dec 6, 2012
From: AMKOR TECHNOLOGY, INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 029422/0178 →
PATENT SECURITY AGREEMENT Recorded Jun 3, 2009
From: AMKOR TECHNOLOGY, INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 022764/0864 →