Reversible top/bottom MEMS package
View Patent ↗A semiconductor device has a base substrate having a plurality of metal traces and a plurality of base vias. An opening is formed through the base substrate. A cover substrate having a plurality of metal traces and a plurality of cover vias is provided. A first die is attached to the first surface of the substrate and positioned over the opening. Side members are coupled to ground planes on the base substrate and cover substrate to form an RF shield around the first die. At least one wirebond having a first end attached to the first die and a second end attached to a metal trace of the base substrate is provided. The at least one wirebond forms a loop wherein a top section of the loop contacts a metal trace of the cover substrate.
1. A semiconductor device comprising:
a base substrate having a plurality of metal traces and a plurality of base vias;
an opening formed through the base substrate;
a cover substrate having a plurality of metal traces and a plurality of cover vias;
at least one die attached to the first surface of the base substrate and positioned over the opening; and
side members coupled to ground planes on the base substrate and cover substrate to form an RF shield around the first die, wherein the side members comprises:
a frame member formed of a non-conductive material;
a first set of conductive vias formed through the frame member, the first set of conductive vias coupled to the ground planes on the base substrate and cover substrate, the first set of conductive vias exposed on a side surface of the frame member; and
a second set of conductive vias formed through the frame member, the second set of conductive vias coupled to the metal traces on the base substrate and cover substrate.
2. A semiconductor device in accordance with claim 1 , wherein the first set of conductive vias are formed on an outer perimeter of the device.
3. A semiconductor device in accordance with claim 1 , wherein the second set of conductive vias are formed on an inner perimeter of the device.
4. A semiconductor device in accordance with claim 1 , wherein at least one of the cover vias connected to a plurality of pads when the cover substrate is attached to an I/O board.
5. A semiconductor device in accordance claim 1 , wherein the second set of conductive vias are I/O pathways.
6. A semiconductor device in accordance with claim 1 , wherein the first die is a transducer.
7. A semiconductor device in accordance with claim 1 , further comprising a second die attached to the first surface of the base substrate.
8. A semiconductor device in accordance with claim 7 , further comprising at least one wire bond coupled to the first die and the second die.
9. A semiconductor device in accordance with claim 1 , wherein the first die is a transducer.
10. A semiconductor device in accordance with claim 9 , wherein the second die is an amplifier.
11. A semiconductor device comprising:
a base substrate having a plurality of metal traces and a plurality of base vias;
an opening formed through the base substrate;
a cover substrate having a plurality of metal traces and a plurality of cover vias;
a first electronic component attached to the first surface of the base substrate and positioned over the opening, wherein the first electronic component is a transducer;
a second electronic component attached to the first surface of the base substrate next to the transducer, wherein the second electronic component is an amplifier;
side members coupled to the base substrate and cover substrate;
a first set of wirebonds wherein each of the first set of wirebonds have a first end attached to the transducer and a second end attached to the amplifier;
a first set of conductive vias formed through the side members along an outer perimeter of the device and coupled to ground planes on the base substrate and cover substrate to form an RF shield around the transducer and amplifier, the first set of conductive vias exposed on a side surface of the side member; and
a second set of conductive vias formed through the side member along an inner perimeter of the device and coupled to the metal traces on the base substrate and the metal traces on the cover substrate to form I/O pathways between the base substrate and cover substrate.
12. A semiconductor device in accordance with claim 11 , wherein the side members comprises:
a frame member;
wherein the first set of conductive vias are formed through the frame member and exposed on a side surface of the frame member.
13. A semiconductor device in accordance with claim 11 , further comprising:
at least one second wirebond having a first end attached to the second electronic component and a second end attached to the metal traces on the base substrate;
wherein the side members comprises:
a frame member; and
wherein the first set of conductive vias are formed through the frame member, the first set of conductive vias coupled to the ground planes on the base substrate and cover substrate to form the RF shield; and
wherein the second set of conductive vias are formed through the frame member, wherein the second set of conductive vias are coupled to the metal traces on the base substrate and the metal traces on the cover substrate to form I/O pathways.
14. A semiconductor device in accordance with claim 11 , wherein at least one of the cover vias forms an interconnect when the cover substrate is attached to an I/O board.
15. A semiconductor device comprising:
a base substrate having a plurality of metal traces, a plurality of base vias, and a plurality of base pads;
a cover substrate having a plurality of metal traces, a plurality of cover vias, and a plurality of cover pads;
an opening formed through the base substrate;
a first die attached to the first surface of the base substrate and positioned over the opening and electrically attach to the metal traces of the base substrate;
a second die attached to the first surface of the base substrate and electrically attach to the metal traces of the base substrate;
side members coupled to ground planes on the base substrate and cover substrate to form an RE shield around the first die and the second die, wherein the side members comprises:
a frame member; and
a first set of conductive vias formed through the frame member and exposed on a side surface of the frame member, the first set of conductive vias coupled to the ground planes on the base substrate and cover substrate to form the RE shield; and
a second set of conductive vias formed through the frame member, wherein the second set of conductive vias are coupled to the metal traces on the base substrate and the metal traces on the cover substrate to form the means to form I/O pathways.
16. A semiconductor device in accordance with claim 15 , wherein at least one of the cover vias connected to the cover pads when the cover substrate is attached to an I/O board.
17. A semiconductor device in accordance with claim 15 , wherein the first die is a transducer.