Land patterns for a semiconductor stacking structure and method therefor

1. A semiconductor device comprising:

a substrate;

a semiconductor die coupled to a first surface of the substrate;

a first plurality of lands on the first surface of the substrate around an encapsulate; and

a second plurality of lands on a second surface of the substrate, wherein a first group of the second plurality of lands have a pitch and a second group of the second plurality of lands have a pitch of a different distance;

wherein each of the first plurality of lands is coupled to a corresponding land of the first group of the second plurality of lands;

wherein the semiconductor die is electrically coupled to at least one of the first plurality of lands and to one of the second group of the second plurality of lands.

2. A semiconductor device in accordance with claim 1 , wherein the pitch of the first group of the second plurality of lands have a larger pitch than the pitch of the second group of the second plurality of lands.

3. A semiconductor device in accordance with claim 1 , wherein the first group of the second plurality of lands are aligned with the first plurality of lands on the first surface of the substrate.

4. A semiconductor device in accordance with claim 1 , wherein a pitch of the first plurality of lands is approximately the same as the pitch of the first group of the second plurality of lands.

5. A semiconductor device in accordance with claim 1 , wherein each of the first plurality of lands is coupled to a corresponding land of the first group of the second plurality of lands by a via formed in the substrate.

6. A semiconductor device in accordance with claim 1 , wherein the second group of the second plurality of lands is positioned below an encapsulant used to encapsulate the semiconductor die.

7. A semiconductor device in accordance with claim 1 , further comprising:

a first via coupled to the semiconductor device;

a second via coupled to at least one of the second group of the second plurality of lands; and

a metal trace formed in the substrate to coupled the first via to the second via to electrically couple the semiconductor die to one of the second group of the second plurality of lands.

8. A semiconductor device comprising:

a substrate;

a semiconductor die coupled to a first surface of the substrate;

a first plurality of lands on the first surface of the substrate around an encapsulate; and

a second plurality of lands on a second surface of the substrate, wherein a first group of the second plurality of lands are positioned below and coupled to the first plurality of lands, and a second group of the second plurality of lands are partially positioned below the semiconductor die;

wherein each of the first plurality of lands is coupled to a corresponding land of the first group of the second plurality of lands, and wherein the semiconductor die is electrically coupled to at least one of the first plurality of lands and to one of the second group of the second plurality of lands;

wherein a pitch of the first group of the second plurality of lands is larger than a pitch of the second group of the second plurality of lands;

wherein a pitch of the first plurality of lands is approximately the same as the pitch of the first group of the second plurality of lands.

9. A semiconductor device in accordance with claim 8 wherein the second group of the second plurality of lands is positioned below an encapsulant used to encapsulate the semiconductor die.

10. A semiconductor device in accordance with claim 8 , wherein each of the first plurality of lands is coupled to a corresponding land of the first group of the second plurality of lands by a via formed in the substrate.

11. A semiconductor device comprising:

a substrate;

a semiconductor die coupled to a first surface of the substrate;

means formed on the first surface of the substrate around an outer perimeter of an encapsulate for providing electrical connections; and

means formed on a second surface of the substrate for providing electrical connections, wherein a first group of means formed on the second surface of the substrate have a first pitch and a second group of means formed on the second surface of the substrate have a second pitch of a different distance;

wherein the semiconductor die is electrically coupled to at least one of the means formed on the first surface and to one of the second group of means formed on the second surface of the substrate.

12. A semiconductor device in accordance with claim 11 , wherein the first pitch is greater than the second pitch.

13. A semiconductor device in accordance with claim 11 , wherein the first group means formed on the second surface of the substrate is aligned with the means formed on the first surface of the substrate.

14. A semiconductor device in accordance with claim 11 , wherein a pitch of the means formed on the first surface of the substrate is approximately equal to the first pitch of the first group of means formed on the second surface of the substrate.

15. A semiconductor device in accordance with claim 11 , wherein each of the means formed on the first surface of the substrate is exclusively coupled to a corresponding first group of means formed on the second surface of the substrate by a via formed in the substrate.

16. A semiconductor device in accordance with claim 11 , further comprising metal traces formed on the substrate to electrically couple the semiconductor die to at least one of the means formed on the first surface.