Semiconductor device and fabricating method thereof
View Patent ↗Disclosed are a semiconductor device capable of efficiently radiating heat of a semiconductor die and a method of fabricating the same. The semiconductor device efficiently radiates the heat by preventing an encapsulant from reaching the semiconductor die by an encapsulant dam so that an upper surface of the semiconductor die is exposed out of the encapsulant. In addition, the semiconductor device is configured to expose a pre-solder ball or a conductive pattern of a substrate through a via of the encapsulant. Therefore, electrical connection between the pre-solder ball and a solder ball of another semiconductor device stacked thereon is easily achieved.
1. A semiconductor device comprising:
a substrate comprising an upper surface;
an encapsulant dam coupled to the upper surface, the encapsulant dam defining an inner region and an outer region of the substrate;
flip chip terminals coupled to the upper surface of the substrate within the inner region;
stacking terminals coupled to the upper surface of the substrate within the outer region;
a semiconductor die within the inner region and coupled to the flip chip terminals; and
an encapsulant within the outer region.
2. The semiconductor device of claim 1 wherein the encapsulant is disposed around an outer periphery of the encapsulant dam.
3. The semiconductor device of claim 1 further comprising pre-solder balls coupled to the stacking terminals.
4. The semiconductor device of claim 3 wherein the encapsulant encloses the pre-solder balls.
5. The semiconductor device of claim 4 wherein the encapsulant comprises via apertures exposing the pre-solder balls.
6. The semiconductor device of claim 3 wherein the pre-solder balls are planarized.
7. The semiconductor device of claim 1 wherein the encapsulant comprises via apertures formed therein to expose the stacking terminals.
8. The semiconductor device of claim 1 , wherein the encapsulant dam comprises solder resist.
9. The semiconductor device of claim 1 , wherein the inner region has a larger area than the semiconductor die.
10. The semiconductor device of claim 1 further comprising conductive bumps coupling bond pads of the semiconductor die to the flip chip terminals.
11. The semiconductor device of claim 10 further comprising an underfill enclosing the conductive bumps.
12. The semiconductor device of claim 11 , wherein the underfill is disposed within the inner region.
13. The semiconductor device of claim 1 , wherein the semiconductor die comprises an inactive surface exposed to the outside.
14. A semiconductor device comprising:
a first semiconductor device comprising:
a first substrate comprising a lower surface; and
lands coupled to the lower surface;
a second semiconductor device comprising:
a second substrate comprising an upper surface;
an encapsulant dam coupled to the upper surface of the second substrate, the encapsulant dam defining an inner region and an outer region of the second substrate;
an encapsulant within the outer region;
stacking terminals coupled to the upper surface of the second substrate within the outer region, wherein the lands of the first semiconductor device are coupled to the stacking terminals through via apertures of the encapsulant.
15. The semiconductor device of claim 14 wherein the via apertures extend entirely through the encapsulant to the stacking terminals, the semiconductor device further comprising:
solder balls extending from the lands to the stacking terminals through the via apertures.
16. The semiconductor device of claim 14 wherein the second semiconductor device further comprises:
pre-solder balls coupled to the stacking terminals,
wherein the first semiconductor device further comprises:
solder balls coupled to the pre-solder balls through the via apertures.
17. A semiconductor device, comprising:
a substrate comprising an upper surface;
an encapsulant dam coupled to the upper surface of the substrate;
a semiconductor die coupled to the upper surface of the substrate within an inner region defined by the encapsulant dam;
an encapsulant coupled to the upper surface of the substrate within an outer region defined by the encapsulant dam; and
stacking terminals coupled to the upper surface of the substrate within the outer region.
18. The semiconductor device of claim 17 further comprising:
pre-solder balls coupled to the stacking terminals; and
via apertures within the encapsulant to expose the pre-solder balls.
19. The semiconductor device of claim 17 further comprising:
via apertures extending entirely though the encapsulant to expose the stacking terminals.