Two-sided wafer escape package

1. A method of forming an electronic component package comprising:

providing an electronic component, the electronic component having a plurality of bond pads formed on a first surface of the electronic component;

forming electrically conductive traces connecting first selected bond pads of the plurality of bond pads on the first surface of the electronic component to corresponding bonding locations on a second surface of the electronic component;

coupling the first surface of the electronic component to a first surface of a lower dielectric strip;

coupling the second surface of the electronic component to a first surface of an upper dielectric strip;

forming lower via apertures through the lower dielectric strip to expose second selected bond pads of the plurality of bond pads on the first surface of the electronic component;

forming upper via apertures through the upper dielectric strip to expose the bonding locations on the second surface of the electronic component;

filling the lower via apertures with an electrically conductive material to form lower vias electrically coupled to the second selected bond pads of the plurality of bond pads on the first surface of the electronic component; and

filling the upper via apertures with an electrically conductive material to form upper vias electrically coupled to the bonding locations on the second surface of the electronic component.

2. The method of forming an electronic component package of claim 1 , further comprising:

forming trace channels in the upper or lower dielectric layer.

3. The method of forming an electronic component package of claim 2 , wherein the trace channels are optimally shaped trace channels.

4. The method of forming an electronic component package of claim 3 further comprising:

applying a metal layer to an inner surface of at least one of said the trace channels to form at least one electrically conductive trace.

5. The method of claim 1 wherein excess electrically conductive material is formed on a second surface of the lower dielectric strip, the method further comprising removing the excess electrically conductive material from the second surface of the lower dielectric strip, further wherein excess electrically conductive material is formed on a second surface of the upper dielectric strip, the method further comprising removing the excess electrically conductive material from the second surface of the upper dielectric strip.

6. The method of claim 5 wherein the removing the excess electrically conductive material from the second surface of the lower dielectric strip and the removing the excess electrically conductive material from the second surface of the upper dielectric strip is performed using an etch process.

7. The method of claim 6 wherein the lower vias extend from the bond pads through the lower dielectric strip to be adjacent the second surface of the lower dielectric strip, further wherein, the upper vias extend from the bonding locations through the upper dielectric strip to be adjacent the second surface of the upper dielectric strip.

8. The method of claim 6 wherein the lower vias extend from the bond pads through the lower dielectric strip to be recessed from the second surface of the lower dielectric strip, further wherein the upper vias extend from the bonding locations through the upper dielectric strip to be recessed from the second surface of the upper dielectric strip.

9. The method of claim 5 further comprising:

inspecting the integrity of the lower vias;

when the lower vias comprise defective lower vias removing the lower vias; and

reapplying the electrically conductive material in the lower via apertures to reform the lower vias;

inspecting the integrity of the upper vias;

when the upper vias comprise defective upper vias removing the upper vias; and

reapplying the electrically conductive material in the upper via apertures to reform the upper vias.

10. The method of claim 1 wherein the coupling a first surface of an electronic component to a first surface of a lower dielectric strip comprises mounting the first surface of the electronic component to the first surface of the lower dielectric strip with an adhesive.

11. The method of claim 1 wherein the coupling a second surface of an electronic component to a first surface of a upper dielectric strip comprises mounting the second surface of the electronic component to the first surface of the upper dielectric strip with an adhesive.

12. A method of forming an electronic component package comprising:

providing an electronic component, the electronic component having a plurality of bond pads formed on a first surface of the electronic component;

forming electrically conductive traces connecting first selected bond pads of the plurality of bond pads on the first surface of the electronic component to corresponding bonding locations on a second surface of the electronic component;

coupling the first surface of the electronic component to a first surface of a lower dielectric strip with an adhesive;

coupling the second surface of the electronic component to a first surface of an upper dielectric strip with an adhesive;

forming lower via apertures through the lower dielectric strip and the adhesive to expose second selected bond pads of the plurality of bond pads on the first surface of the electronic component;

forming upper via apertures through the upper dielectric strip to expose the bonding locations on the second surface of the electronic component;

filling the lower via apertures with an electrically conductive material to form lower vias electrically coupled to the second selected bond pads of the plurality of bond pads on the first surface of the electronic component; and

filling the upper via apertures with an electrically conductive material to form upper vias electrically coupled to the bonding locations on the second surface of the electronic component.