Semiconductor package having through holes
View Patent ↗Disclosed is a semiconductor package. The semiconductor package is configured to form a plurality of through holes for forming a through silicon via at once using a sawing device used for wafer sawing instead of a separate laser drilling equipment or a deep reactive ion etching (DRIE) equipment. Accordingly, the semiconductor package saves fabricating time and increases fabrication yield, saves costs for a laser drilling equipment or a DRIE equipment, and prevents various defects generated in an inner portion of a through hole in the case of using the laser drilling equipment or the DRIE equipment.
1. A semiconductor package, comprising:
a semiconductor die comprising:
a first surface;
a second surface opposite to the first surface;
a plurality of bond pads on the first surface; and
a passivation layer exposing the bond pads;
first through holes perpendicularly penetrating the bond pads and the first surface;
second through holes perpendicularly penetrating the passivation layer and the first surface between adjacent bond pads of the bond pads;
a photosensitive layer pattern formed on the passivation layer and in the second through holes, and having pattern holes exposing the first through holes and portions of the bond pads connected with the first through holes; and
electrically conductive vias extended inside the first through holes from the photosensitive layer pattern via the pattern holes.
2. The semiconductor package of claim 1 , wherein the bond pads are arranged along a periphery of the first surface of the semiconductor die.
3. The semiconductor package of claim 1 , wherein the first and second through holes are formed by sawing the semiconductor die along sawing lines passing through the bond pads in a direction from the first surface to the second surface, the second through holes being positioned between the adjacent first through holes.
4. The semiconductor package of claim 1 , wherein the photosensitive layer pattern formed in the second through holes electrically insulates the electrically conductive vias from one another.
5. The semiconductor package of claim 1 , wherein the electrically conductive vias comprise:
first electrodes formed on the photosensitive layer pattern;
second electrodes electrically coupled to the first electrodes and formed in the pattern holes; and
third electrodes electrically coupled to the second electrodes and formed in the first through holes.
6. The semiconductor package of claim 5 , wherein the second electrodes are electrically coupled to the bond pads.
7. The semiconductor package of claim 5 , wherein the first electrodes, the second electrodes and the third electrodes are integrally formed.
8. The semiconductor package of claim 5 , wherein the third electrodes are rectangular.
9. The semiconductor package of claim 5 , wherein the electrically conductive vias further comprise fourth electrodes formed on the second surface of the semiconductor die and electrically coupled to the third electrodes.
10. A semiconductor package, comprising:
a semiconductor die comprising:
a first surface;
a second surface opposite to the first surface;
a plurality of bond pads on the first surface; and
a passivation layer exposing the bond pads;
trenches formed in the first surface of the semiconductor die, the trenches comprising:
first trench portions perpendicularly penetrating the bond pads and the first surface;
second trench portions perpendicularly penetrating the passivation layer and the first surface between adjacent bond pads of the bond pads;
a photosensitive layer pattern formed on the passivation layer and in the second trench portions, and having pattern holes exposing the first trench portions and portions of the bond pads connected with the first trench portions; and
electrically conductive vias extended inside the first trench portions from the photosensitive layer pattern via the pattern holes.
11. The semiconductor package of claim 10 , wherein the trenches are formed by sawing the semiconductor die along sawing lines passing through the bond pads in a direction from the first surface to the second surface.
12. The semiconductor package of claim 10 , wherein the second trench portions are positioned between the adjacent first trench portions.
13. A semiconductor package, comprising:
a semiconductor die comprising:
a first surface;
a second surface opposite to the first surface;
a plurality of bond pads on the first surface; and
a passivation layer exposing the bond pads;
first trench portions perpendicularly penetrating the bond pads and the first surface;
second trench portions perpendicularly penetrating the passivation layer and the first surface between adjacent bond pads of the bond pads;
a photosensitive layer pattern formed on the passivation layer and in the second trench portions, and having pattern holes exposing the first trench portions and portions of the bond pads connected with the first trench portions; and
electrically conductive vias extended inside the first trench portions from the photosensitive layer pattern via the pattern holes.
14. The semiconductor package of claim 13 , wherein the bond pads are arranged along a periphery of the first surface of the semiconductor die.
15. The semiconductor package of claim 13 , wherein the first and second trench portions are formed by sawing the semiconductor die along sawing lines passing through the bond pads in a direction from the first surface to the second surface, the second trench portions being positioned between the adjacent first trench portions.
16. The semiconductor package of claim 13 , wherein the photosensitive layer pattern formed in the second trench portions electrically insulates the electrically conductive vias from one another.
17. The semiconductor package of claim 13 , wherein the electrically conductive vias comprise:
first electrodes formed on the photosensitive layer pattern;
second electrodes electrically coupled to the first electrodes and formed in the pattern holes; and
third electrodes electrically coupled to the second electrodes and formed in the first trench portions.
18. The semiconductor package of claim 17 , wherein the second electrodes are electrically coupled to the bond pads.
19. The semiconductor package of claim 17 , wherein the first electrodes, the second electrodes and the third electrodes are integrally formed.
20. The semiconductor package of claim 17 , wherein the third electrodes are rectangular.