Method of making an integrated circuit package
View Patent ↗Packages for an integrated circuit die and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wires, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad and the contacts have side surfaces which include reentrant portions and asperities to engage the encapsulant. A method of making a package includes providing a metal leadframe having a die pad in a rectangular frame. Tabs extend from the frame toward the die pad. The die pad and tabs have side surfaces with reentrant portions and asperities. A die is attached to the die pad. The die is electrically connected to the tabs. An encapsulant is applied to the upper and side surfaces of the leadframe. Finally, the leadframe is cut in situ so that the die pad and tabs are severed from the frame, the sides of the package are formed, and the package is severed from the leadframe.
1. A method of making a leadframe for an integrated circuit chip package, comprising:
chemically etching the leadframe to include:
a frame;
a die pad integrally connected to the frame and defining opposed first and second die pad surfaces, and at least one die pad side surface extending between the first and second die pad surfaces;
a plurality of tabs connected to the frame and extending toward the die pad in spaced relation thereto, each of the tabs defining opposed first and second tab surfaces and only three tab side surfaces extending between the first and second tab surfaces; and
a reentrant portion disposed within at least a portion of the die pad side surface and within each of the tab side surfaces.
2. The method of claim 1 wherein the leadframe is etched such that:
the die pad defines at least four die pad side surfaces;
a reentrant portion is disposed within each of the at least four die pad side surfaces of the die pad.
3. The method of claim 2 wherein the leadframe is etched such that each of the reentrant portions defines a peak which extends from a respective one of the die pad and tab side surfaces.
4. The method of claim 3 wherein the leadframe is etched such that asperities are formed upon the peak extending from each of the die pad and tab side surfaces.
5. The method of claim 2 wherein the leadframe is etched such that each of the reentrant portions defines a depression within a respective one of the die pad and tab side surfaces.
6. The method of claim 5 wherein the leadframe is etched such that asperities are formed within the depression in each of the die pad and tab side surfaces.
7. The method of claim 2 wherein the leadframe is etched such that each of the reentrant portions defines a lip which extends along a respective one of the die pad and tab side surfaces.
8. A method of making a leadframe for an integrated circuit chip package, comprising:
chemically etching the leadframe to include:
a die pad defining opposed first and second die pad surfaces, and at least one die pad side surface extending between the first and second die pad surfaces;
a plurality of tabs extending toward the die pad in spaced relation thereto, each of the tabs defining opposed first and second tab surfaces and only three tab side surfaces extending between the first and second tab surfaces; and
a locking portion disposed within at least a portion of the die pad side surface and within each of the tab side surfaces.
9. The method of claim 8 wherein the leadframe is etched such that:
the die pad defines at least four die pad side surfaces; and
the locking portion is disposed within each of the at least four die pad side surfaces of the die pad.
10. The method of claim 9 wherein the leadframe is etched such that each of the locking portions defines a peak which extends from a respective one of the die pad and tab side surfaces.
11. The method of claim 10 wherein the leadframe is etched such that asperities are formed upon the peak extending from each of the die pad and tab side surfaces.
12. The method of claim 9 wherein the leadframe is etched such that each of the locking portions defines a depression within a respective one of the die pad and tab side surfaces.
13. The method of claim 12 wherein the leadframe is etched such that asperities are formed within the depression in each of the die pad and tab side surfaces.
14. The method of claim 9 wherein the leadframe is etched such that each of the locking portions defines a lip which extends along a respective one of the die pad and tab side surfaces.
15. A method of making a leadframe for an integrated circuit chip package, comprising:
forming a die pad which defines opposed first and second die pad surfaces, and at least one die pad side surface extending between the first and second die pad surfaces;
forming a plurality of tabs which extend toward the die pad in spaced relation thereto, each of the tabs defining opposed first and second tab surfaces and only three tab side surfaces extending between the first and second tab surfaces; and
forming a means within at least a portion of the die pad side surface and within each of the tab side surfaces for providing a mechanical interlock to a block of a hardened encapsulant material.
16. The method of claim 15 wherein:
the die pad is formed to define at least four die pad side surfaces; and
the interlock means is formed within each of the at least four die pad side surfaces of the die pad.
17. The method of claim 15 wherein the die pad, the tabs, and the mechanical interlock means are each formed by a chemical etching process.