Methods of forming conductive structures including titanium-tungsten base layers and related structures

1. A method of metallizing an integrated circuit chip including a substrate, a conductive pad on the substrate, and an insulating layer on the substrate wherein the insulating layer has a via hole therein exposing a portion of the conductive pad, the method comprising:

forming a conductive structure on the insulating layer and on the exposed portion of the conductive pad, the conductive structure including a base layer comprising titanium-tungsten (TiW) and a conduction layer comprising at least one of aluminum and/or copper, wherein the base layer of the conductive structure is between the conduction layer and the insulating layer wherein a portion of the conductive pad is exposed between the insulating layer and the conductive structure wherein forming the conductive structure on the insulating layer comprises,

forming a layer of titanium-tungsten on the insulating layer and on the exposed portions of the conductive pad,

forming the conduction layer comprising at least one of aluminum and/or copper on the layer of titanium-tungsten so that portions of the layer of titanium-tungsten layer are exposed, and

after forming the conduction layer comprising at least one of aluminum and/or copper, removing portions of the layer of titanium-tungsten exposed by the conduction layer comprising at least one of aluminum and/or copper.

2. A method according to claim 1 wherein removing portions of the layer of titanium-tungsten comprises etching the layer of titanium-tungsten using hydrogen peroxide.

3. A method according to claim 1 wherein removing portions of the layer of titanium-tungsten comprises etching the layer of titanium-tungsten using a mixture including hydrogen peroxide, potassium sulfate, benzotriazole, and sulfo-salicylic acid.

4. A method according to claim 1 wherein the base layer of the conductive structure includes a lip extending beyond the conduction layer of the conductive structure after removing portions of the layer of titanium-tungsten.

5. A method according to claim 1 wherein the conductive pad comprises at least one of aluminum and/or copper.

6. A method according to claim 1 wherein the insulating layer comprises at least one of benzocyclobutene, polyimide, silicon oxide, silicon nitride, and/or silicon oxynitride.

7. A method according to claim 1 wherein the conduction layer of the conductive structure comprises an aluminum layer and wherein the base layer of the conductive structure is between the conduction layer and the substrate.

8. A method of metallizing an integrated circuit chip including a substrate, a conductive pad on the substrate, and an insulating layer on the substrate wherein the insulating layer has a via hole therein exposing a portion of the conductive pad, the method comprising:

forming a conductive structure on the insulating layer and on the exposed portion of the conductive pad, the conductive structure including a base layer comprising titanium-tungsten (TiW) and a conduction layer comprising at least one of aluminum and/or copper, wherein the base layer of the conductive structure is between the conduction layer and the insulating layer wherein a portion of the conductive pad is exposed between the insulating layer and the conductive structure;

forming a second insulating layer on the conductive structure and on the first insulating layer so that the conductive structure is between the first and second insulating layers; and

forming a second via hole in the second insulating layer exposing a portion of the conductive structure wherein the first and second via holes are offset.

9. A method according to claim 8 further comprising:

forming an interconnection structure on the exposed portion of the conductive structure.

10. A method according to claim 9 further comprising:

forming an under bump metallurgy layer between the interconnection structure and the exposed portion of the conductive structure.

11. A method according to claim 9 wherein the interconnection structure comprises solder.

12. A method of metallizing an integrated circuit chip including a substrate, a conductive pad on the substrate, and an insulating layer on the substrate wherein the insulating layer has a via hole therein exposing a portion of the conductive pad, the method comprising:

forming a conductive structure on the insulating layer and on the exposed portion of the conductive pad, the conductive structure including a base layer comprising titanium-tungsten (TiW) and a conduction layer comprising an aluminum layer, wherein the base layer of the conductive structure is between the conduction layer and the insulating layer and between the conduction layer and the substrate and, wherein forming the conductive structure on the insulating layer comprises,

forming a layer of titanium-tungsten on the insulating layer and on the exposed portions of the conductive pad,

forming the conduction layer comprising at least one of aluminum and/or copper on the layer of titanium-tungsten so that portions of the layer of titanium-tungsten layer are exposed, and

after forming the conduction layer comprising at least one of aluminum and/or copper, removing portions of the layer of titanium-tungsten exposed by the conduction layer comprising at least one of aluminum and/or copper.

13. A method according to claim 12 wherein removing portions of the layer of titanium-tungsten comprises etching the layer of titanium-tungsten using hydrogen peroxide.

14. A method according to claim 12 wherein removing portions of the layer of titanium-tungsten comprises etching the layer of titanium-tungsten using a mixture including hydrogen peroxide, potassium sulfate, benzotriazole, and sulfo-salicylic acid.

15. A method according to claim 12 wherein the base layer of the conductive structure includes a lip extending beyond the conduction layer of the conductive structure after removing portions of the layer of titanium-tungsten.

16. A method according to claim 12 wherein the conductive pad comprises at least one of aluminum and/or copper.

17. A method according to claim 12 wherein the conduction layer of the conductive structure further comprises a titanium layer between the aluminum layer and the base layer of the conductive structure.

18. A method according to claim 12 wherein a portion of the conductive pad is exposed between the insulating layer and the conductive structure.

19. A method according to claim 12 wherein the insulating layer comprises at least one of benzocyclobutene, polyimide, silicon oxide, silicon nitride, and/or silicon oxynitride.

20. A method of metallizing an integrated circuit chip including a substrate, a conductive pad on the substrate, and an insulating layer on the substrate wherein the insulating layer has a via hole therein exposing a portion of the conductive pad, the method comprising:

forming a conductive structure on the insulating layer and on the exposed portion of the conductive pad, the conductive structure including a base layer comprising titanium-tungsten (TiW) and a conduction layer comprising an aluminum layer, wherein the base layer of the conductive structure is between the conduction layer and the insulating layer and between the conduction layer and the substrate;

wherein the conduction layer of the conductive structure further comprises a titanium layer between the aluminum layer and the base layer of the conductive structure.

21. A method of metallizing an integrated circuit chip including a substrate, and an insulating layer on the substrate, the method comprising:

forming a conductive structure on the insulating layer, the conductive structure including a base layer comprising titanium-tungsten (TiW) and a conduction layer comprising at least one of aluminum and/or copper, wherein the base layer of the conductive structure is between the conduction layer and the insulating layer, wherein forming the conductive structure on the insulating layer comprises,

forming a layer of titanium-tungsten on the insulating layer,

after forming the layer of titanium-tungsten, forming the conduction layer comprising at least one of aluminum and/or copper on the layer of titanium-tungsten so that portions of the layer of titanium-tungsten layer are exposed, and

after forming the conduction layer comprising at least one of aluminum and/or copper, removing portions of the layer of titanium-tungsten exposed by the conduction layer comprising at least one of aluminum and/or copper, wherein the base layer of the conductive structure includes a lip extending beyond the conduction layer of the conductive structure after removing portions of the layer of titanium-tungsten.

22. A method according to claim 21 wherein removing portions of the layer of titanium-tungsten comprises etching the layer of titanium-tungsten using hydrogen peroxide.

23. A method according to claim 21 wherein removing portions of the layer of titanium-tungsten comprises etching the layer of titanium-tungsten using a mixture including hydrogen peroxide, potassium sulfate, benzotriazole, and sulfo-salicylic acid.

24. A method according to claim 21 wherein the electronic device includes a conductive pad on the substrate, wherein the insulating layer has a via hole therein exposing a portion of the conductive pad, and wherein forming the conductive structure includes forming the conductive structure on the insulating layer and on exposed portions of the conductive pad.

25. A method according to claim 24 wherein the conductive pad comprises at least one of aluminum and/or copper.

26. A method according to claim 24 wherein a portion of the conductive pad is exposed between the insulating layer and the conductive structure.

27. A method according to claim 21 further comprising:

forming a second insulating layer on the conductive structure and on the first insulating layer so that the conductive structure is between the first and second insulating layers; and

forming a second via hole in the second insulating layer exposing a portion of the conductive structure.

28. A method according to claim 27 further comprising:

forming an interconnection structure on the exposed portion of the conductive structure.

29. A method according to claim 28 further comprising:

forming an under bump metallurgy layer between the interconnection structure and the exposed portion of the conductive structure.

30. A method according to claim 28 wherein the interconnection structure comprises solder.

31. A method according to claim 21 wherein the conduction layer of the conductive structure comprises an aluminum layer and wherein the layer of titanium-tungsten is between the aluminum layer and the substrate.

32. A method according to claim 31 wherein the conduction layer of the conductive structure further comprises a titanium layer between the aluminum layer and the base layer of the conductive structure.

33. A method according to claim 21 wherein the insulating layer comprises at least one of benzocyclobutene, polyimide, silicon oxide, silicon nitride, and/or silicon oxynitride.

34. A method of forming an electronic device, the method comprising:

forming a continuous metal base layer on an insulating layer;

forming a metal wiring layer on a portion of the continuous metal base layer so that portions of the continuous metal base layer are free of the metal wiring layer and so that the continuous metal base layer is between the metal wiring layer and the insulating layer; and

removing portions of the continuous metal base layer free of the metal wiring layer to provide a patterned metal base layer between the metal wiring layer and the insulating layer wherein the patterned metal base layer includes a lip extending beyond the metal wiring layer.

35. A method according to claim 34 wherein the continuous metal base layer is maintained free of a mask other than the metal wiring layer while removing portions of the continuous metal base layer.

36. A method according to claim 34 wherein the continuous metal base layer comprises titanium-tungsten.

37. A method according to claim 36 wherein the metal wiring layer comprises an aluminum layer and wherein the continuous metal base layer comprising titanium-tungsten is between the aluminum layer and the insulating layer.

38. A method according to claim 37 wherein the metal wiring layer includes a titanium layer between the aluminum layer and the metal base layer.

39. A method of metallizing an integrated circuit chip including a substrate, a conductive pad on the substrate, and an insulating layer on the substrate wherein the insulating layer has a via hole therein exposing a portion of the conductive pad, the method comprising:

forming a conductive structure on the insulating layer and on the exposed portion of the conductive pad, the conductive structure including a base layer comprising titanium-tungsten (TiW) and a conduction layer comprising an aluminum layer, wherein the base layer of the conductive structure is between the conduction layer and the insulating layer and between the conduction layer and the substrate;

forming a second insulating layer on the conductive structure and on the first insulating layer so that the conductive structure is between the first and second insulating layers; and

forming a second via hole in the second insulating layer exposing a portion of the conductive structure wherein the first and second via holes are offset.

40. A method according to claim 39 further comprising:

forming an interconnection structure on the exposed portion of the conductive structure.

41. A method according to claim 40 further comprising:

forming an under bump metallurgy layer between the interconnection structure and the exposed portion of the conductive structure.

42. A method according to claim 40 wherein the interconnection structure comprises solder.