Solder structures including barrier layers with nickel and/or copper
View Patent ↗An electronic device may include an electronic substrate, and an under bump seed metallurgy layer on the electronic substrate. A barrier layer may be provided on the under bump seed metallurgy layer so that the under bump seed metallurgy layer is between the barrier layer and the electronic substrate, and the barrier layer may include nickel and/or copper. Moreover, portions of the under bump seed metallurgy layer may be undercut relative to portions of the barrier layer. In addition, a solder layer may be provided on the barrier layer so that the barrier layer is between the solder layer and the under bump seed metallurgy layer.
1. An electronic device comprising:
an electronic substrate;
an under bump seed metallurgy layer on the electronic substrate;
a barrier layer on the under bump seed metallurgy layer so that the under bump seed metallurgy layer is between the barrier layer and the electronic substrate, wherein the barrier layer comprises nickel and/or copper, and wherein portions of the under bump seed metallurgy layer are undercut relative to portions of the barrier layer; and
a solder layer on the barrier layer so that the barrier layer is between the solder layer and the under bump seed metallurgy layer;
wherein the barrier layer comprises a nickel layer and a copper layer, and wherein the copper layer is between the under bump seed metallurgy layer and the nickel layer.
2. An electronic device according to claim 1 wherein the barrier layer comprises a nickel layer having a thickness in the range of about 1 μm (micrometer) to about 5 μm (micrometer).
3. An electronic device according to claim 2 wherein the barrier layer has a thickness in the range of about 1.5 μm (micrometer) to about 5 μm (micrometer).
4. An electronic device according to claim 1 wherein the copper layer has a thickness greater than about 5 μm (micrometer).
5. An electronic device according to claim 4 wherein the nickel layer has a thickness in the range of about 1.5 μm (micrometer) to about 5 μm (micrometer).
6. An electronic device according to claim 1 wherein the solder layer comprises a lead-free solder.
7. An electronic device according to claim 1 wherein the solder layer comprises tin and at least one of silver, bismuth, copper, indium, antimony, gold, and/or zinc.
8. An electronic device according to claim 7 wherein a weight percent of tin in the solder layer is greater than about 95 weight percent.
9. An electronic device according to claim 1 wherein the solder layer comprises a first layer of tin and a second layer of silver, bismuth, copper, indium, antimony, gold, and/or zinc.
10. An electronic device according to claim 9 wherein the first layer is between the second layer and the barrier layer.
11. An electronic device according to claim 9 wherein the first layer of tin is greater than about 95 weight percent of the solder layer.
12. An electronic device according to claim 1 wherein the under bump seed metallurgy layer comprises an adhesion layer and a conduction layer and wherein the adhesion and conduction layers comprise different materials.
13. An electronic device according to claim 12 wherein the adhesion layer comprises titanium, titanium-tungsten, titanium nitride, and/or chromium, and wherein the conduction layer comprises copper, silver, and/or gold.
14. An electronic device according to claim 1 wherein the barrier layer comprises a copper layer, and wherein the copper layer has a thickness greater than about 5 μm (micrometer).
15. An electronic device comprising:
an electronic substrate;
an under bump seed metallurgy layer on the electronic substrate;
a barrier layer on the under bump seed metallurgy layer so that the under bump seed metallurgy layer is between the barrier layer and the electronic substrate, wherein the barrier layer comprises nickel and/or copper, and wherein the barrier layer defines a lip portion that extends laterally beyond portions of the under bump seed metallurgy layer wherein the barrier layer comprises a nickel layer and a copper layer, and wherein the copper layer is between the under bump seed metallurgy layer and the nickel layer; and
a solder layer on the barrier layer so that the barrier layer is between the solder layer and the under bump seed metallurgy layer.
16. An electronic device according to claim 15 wherein the barrier layer comprises a nickel layer having a thickness in the range of about 1 μm (micrometer) to about 5 μm (micrometer).
17. An electronic device according to claim 15 wherein the copper layer has a thickness greater than about 5 μm (micrometer).
18. An electronic device according to claim 17 wherein the nickel layer has a thickness in the range of about 1.5 μm (micrometer) to about 5 μm (micrometer).