Flip chip bump structure and fabrication method
View Patent ↗A method includes forming a patterned buildup layer on a first surface of a dielectric layer, the patterned buildup layer including a patterned buildup layer opening exposing a trace coupled to the dielectric layer. A conductor layer is flash plated on the patterned buildup layer and within the patterned buildup layer opening. The patterned buildup layer opening is filled with a blanket conductive filler layer. The blanket conductive filler layer and the conductor layer are planarized to form a flip chip bump.
1. A flip chip bump structure comprising:
a dielectric layer;
a trace coupled to the dielectric layer;
a patterned buildup layer on a first surface of the dielectric layer, the patterned buildup layer comprising a patterned buildup layer opening exposing the trace;
a flip chip bump in the patterned buildup layer opening, the flip chip bump comprising a portion of a blanket conductive filler layer remaining in the patterned buildup layer opening, the flip chip bump further comprising an exterior surface that is coplanar with a first surface of the patterned buildup layer;
a portion of a conductor layer remaining in the patterned buildup layer opening;
a lower circuit pattern coupled to a second surface of the dielectric layer, the lower circuit pattern comprising a land; and
an interconnection ball directly on the land.
2. The flip chip bump structure of claim 1 further comprising:
an electronic component that comprises an active surface comprising a bond pad, the bond pad being physically and electrically coupled to the flip chip bump.
3. A flip chip bump structure comprising:
a dielectric layer;
a trace coupled to the dielectric layer;
a patterned buildup layer on a first surface of the dielectric layer, the patterned buildup layer comprising a patterned buildup layer opening exposing the trace, the patterned buildup layer opening having a width less than a width of the trace; and
a flip chip bump in the patterned buildup layer opening and coupled to the trace, the flip chip bump being entirely cylindrical and having a uniform diameter less than the width of the patterned buildup layer opening.
4. The flip chip bump structure of claim 3 further comprising a conductor layer portion, the flip chip bump being coupled to the trace by the conductor layer portion.
5. The flip chip bump structure of claim 3 further comprising an upper circuit pattern comprising the trace and a second trace, the patterned buildup layer covering and electrically isolating the second trace.
6. The flip chip bump structure of claim 3 wherein the trace is embedded in the dielectric layer.
7. The flip chip bump structure of claim 3 wherein the diameter of the flip chip bump is greater than the width of the trace.
8. The flip chip bump structure of claim 3 wherein the patterned buildup layer opening is a rectangular channel.
9. The flip chip bump structure of claim 3 wherein the patterned buildup layer opening is a cylindrical opening.
10. The flip chip bump structure of claim 3 wherein the flip chip bump is spaced apart from the patterned buildup layer.
11. The flip chip bump structure of claim 3 wherein a gap exists between the flip chip bump and the patterned buildup dielectric layer.
12. The flip chip bump structure of claim 3 wherein the flip chip bump comprises copper.
13. The flip chip bump structure of claim 3 wherein the flip chip bump further comprises an exterior surface that is coplanar with a first surface of the patterned buildup layer.
14. A flip chip bump structure comprising:
a dielectric layer;
a trace coupled to the dielectric layer;
a patterned buildup layer on a first surface of the dielectric layer, the patterned buildup layer comprising a patterned buildup layer opening exposing the trace; and
a flip chip bump in the patterned buildup layer opening and coupled to the trace, the flip chip bump being entirely cylindrical and having a uniform diameter less than a width of the patterned buildup layer opening, wherein the flip chip bump protrudes outwards and beyond the patterned buildup layer.
15. The flip chip bump structure of claim 14 wherein the width of the patterned buildup layer opening is larger than a width of the trace.
16. A flip chip bump structure comprising:
a dielectric layer;
a trace coupled to the dielectric layer;
a patterned buildup layer on a first surface of the dielectric layer, the patterned buildup layer comprising a patterned buildup layer opening exposing the trace, the patterned buildup layer opening having a uniform width;
a conductor layer on the patterned buildup layer and within the patterned buildup layer opening;
a patterned upper resist on the conductor layer, the patterned upper resist comprising a flip chip bump opening directly above the trace exposed through the patterned buildup layer opening; and
a conductive layer filling the flip chip bump opening.
17. The flip chip bump structure of claim 16 wherein the flip chip bump opening has a diameter less than the width of the patterned buildup layer opening.
18. The flip chip bump structure of claim 16 wherein the flip chip bump opening has a diameter greater than the width of the patterned buildup layer opening.