Semiconductor package and method of manufacturing the same which reduces warpage

1. A semiconductor package comprising:

a semiconductor die having a first surface having an integrated circuit formed face and a second surface opposite the first surface, the second surface being coated with a coating material which is exposed, the coating material covering approximately an entire surface area of the second surface of the semiconductor die;

a substrate having an aperture and at least one air vent formed in a surface of thereof, the semiconductor die placed in the aperture;

an encapsulant encapsulating the integrated circuit formed face of the semiconductor die placed in the cavity and sidewalls of the semiconductor die; and

electrical connection members coupled to the semiconductor die and substrate for signal transfer between the semiconductor die and substrate.

2. A semiconductor package in accordance with claim 1 wherein the encapsulant covers sidewalls of the coating material.

3. A semiconductor package in accordance with claim 1 wherein the coating material is coplanar to the first surface of the semiconductor die.

4. A semiconductor package in accordance with claim 1 wherein the coating material reduces warpage of the semiconductor package.

5. A semiconductor package in accordance with claim 1 wherein the coating material has a coefficient of thermal expansion which reduces warpage of the semiconductor package.

6. A semiconductor package in accordance with claim 1 wherein the coating material and the encapsulant have similar coefficients of thermal expansion.

7. A semiconductor package comprising:

a semiconductor die having a first face which is an integrated circuit formed face and a second face opposite the first face;

a coating material coupled to the second face of the semiconductor die, the coating material being exposed and covering approximately an entire surface area of the second face of the semiconductor die;

a substrate having a cavity and at least one air vent formed in a surface thereof, the semiconductor die placed in the cavity;

means for encapsulating the first face of the semiconductor die placed in the cavity and sidewalls of the semiconductor die; and

means for coupling the semiconductor die and the substrate for signal transfer between the semiconductor die and the substrate.

8. A semiconductor package in accordance with claim 7 further comprising means coupled to the substrate for connecting the semiconductor package to an external device.

9. A semiconductor package is accordance with claim 8 wherein the means coupled to the substrate comprises conductive balls attached to ball lands of the substrate for connection to an external device.

10. A semiconductor package in accordance with claim 7 wherein the means for coupling the semiconductor die and the substrate comprises:

bond pads formed on the semiconductor die;

bond fingers formed on the substrate; and

conductive wiring coupled to the bond pads and the bond fingers for signal transfer between the semiconductor die and the substrate.

11. A method for manufacturing a semiconductor package comprising:

providing a semiconductor die having a first face which is an integrated circuit formed face and a second face opposite the first face;

applying a coating material to the second face of the semiconductor die, a top surface of the coating material being exposed and covering approximately an entire surface area of the second face of the semiconductor die;

providing a substrate having an aperture in which the semiconductor die is placed;

forming air vents in the substrate by removing a portion of a solder resist coated with the coating material of the semiconductor die;

encapsulating the first face of the semiconductor die placed in the cavity and sidewalls of the semiconductor die;

coupling the semiconductor die to the substrate for signal transfer between the semiconductor die and the substrate; and

providing terminal members coupled to the substrate for connecting the semiconductor package to an external device.

12. The method of claim 11 wherein the conductor die is positioned in the cavity so sidewalls of the semiconductor die are not in contact with the substrate.

13. A method of fabricating a semiconductor package, comprising the steps of:

grinding a backside of a wafer to a predetermined thickness;

applying a coating material on the backside of the wafer;

sawing the wafer into semiconductor dies of individual units;

attaching a cover tape to a backside of a substrate having a cavity at a central part thereof;

forming air vents in the substrate by removing a portion of a solder resist coated with the coating material of the semiconductor die;

inserting one of the sawed semiconductor dies in the cavity of the substrate so as to be attached to the cover tape;

connecting bond pads of the semiconductor die electrically to bond fingers of the substrate, respectively; and

encapsulating an integrated circuit formed face of the semiconductor die with an encapsulant.

14. The method of claim 13 wherein the coating material is coated on the wafer using one of spin coating, stencil printing, sputtering, tape attach, plating, and combinations thereof.

15. The method of claim 13 further comprising providing terminal members coupled to the substrate for connecting the semiconductor package to an external device.

16. The method of claim 15 wherein the terminal members are conductive balls coupled to ball lands of the substrate for connecting the semiconductor package to an external device.