Thermally enhanced chip scale lead on chip semiconductor package and method of making same
View Patent ↗A thermally enhanced, chip-scale, Lead-on Chip (“LOC”) semiconductor packages includes a substrate having a plurality of metal lead fingers in it. A semiconductor chip having an active surface with a plurality of ground, power, and signal connection pads thereon is mounted on an upper surface of the substrate in a flip-chip electrical connection with the lead fingers. A plurality of the ground and/or the power connection pads on the chip are located in a central region thereof. Corresponding metal grounding and/or power lands are formed in the substrate at positions corresponding to the centrally located ground and/or power pads on the chip. The ground and power pads on the chip are connected to corresponding ones of the grounding and power lands in the substrate in a flip-chip connection, and a lower surface of the lands is exposed to the environment through a lower surface of the semiconductor package for connection to an external heat sink. The lands can be connected to selected ones of the lead fingers, and/or combined with one another for even greater thermal and electrical conductivity.
1. A semiconductor package, comprising:
a substrate comprising:
at least one land defining opposed top and bottom land surfaces;
a plurality of lead fingers disposed about the land, each of the lead fingers defining opposed top and bottom lead surfaces;
a semiconductor chip comprising:
an active surface; and
a plurality of connection pads disposed on the active surface;
at least one of the connection pads being positioned over and conductively connected to the land, with at least one of the connection pads being positioned over and electrically connected to at least one of the lead fingers;
a package body at least partially encapsulating the substrate and the semiconductor chip such that the bottom lead surfaces of the lead fingers are each exposed in a bottom surface of the body.
2. The semiconductor package of claim 1 wherein at least one of the lead fingers is connected to the land.
3. The semiconductor package of claim 1 wherein at least one of the connection pads is positioned over and electrically connected to the land.
4. The semiconductor package of claim 1 wherein at least one of the connection pads is positioned over and in thermal communication with the land.
5. The semiconductor package of claim 1 wherein each of the lead fingers and the land are formed to include a recessed shoulder therein for enhancing the mechanical interlock thereof to the package body.
6. The semiconductor package of claim 1 wherein at least some of the lead fingers each define an angled portion.
7. The semiconductor package of claim 1 wherein:
each of the lead fingers defines an outer end; and
the package body is configured such that the outer end of each of the lead fingers is exposed in a respective one of multiple side surfaces defined by the body.
8. A semiconductor package, comprising:
a substrate comprising:
first and second lands disposed in spaced relation to each other, the first land defining opposed top and bottom first land surfaces and the second land defining opposed top and bottom second land surfaces;
a plurality of lead fingers disposed about the first and second lands, each of the lead fingers defining opposed top and bottom lead surfaces;
a semiconductor chip comprising:
an active surface; and
a plurality of connection pads disposed on the active surface;
at least one of the connection pads being positioned over and conductively connected to the first land, with at least one of the connection pads being positioned over and conductively connected to the second land and at least one of the connection pads being positioned over and electrically connected to at least one of the lead fingers;
a package body at least partially encapsulating the substrate and the semiconductor chip such that the bottom lead surfaces of the lead fingers are each exposed in a bottom surface of the body.
9. The semiconductor package of claim 8 wherein at least two of the lead fingers are connected to respective ones of the first and second lands.
10. The semiconductor package of claim 8 wherein:
at least one of the connection pads is positioned over and electrically connected to the first land; and
at least one of the connection pads is positioned over and electrically connected to the second land.
11. The semiconductor package of claim 8 wherein:
at least one of the connection pads is positioned over and electrically connected to a respective one of the first and second lands; and
at least one of the connection pads is positioned over and in thermal communication with a respective one of the first and second lands.
12. The semiconductor package of claim 8 wherein each of the lead fingers, the first land, and the second land are formed to include a recessed shoulder therein for enhancing the mechanical interlock thereof to the package body.
13. The semiconductor package of claim 8 wherein at least some of the lead fingers each define an angled portion.
14. The semiconductor package of claim 8 wherein:
each of the lead fingers defines an outer end; and
the package body is configured such that the outer end of each of the lead fingers is substantially flush with a respective one of multiple side surfaces defined by the body.
15. A semiconductor package, comprising:
a substrate, comprising:
a land defining opposed top and bottom land surfaces and a plurality of land fingers;
a plurality of lead fingers disposed proximate to the land, each of the lead fingers defining opposed top and bottom lead surfaces;
a semiconductor chip comprising:
an active surface; and
a plurality of connection pads which extend along the active surface in spaced, generally parallel rows;
at least one of the connection pads being positioned over and conductively connected to at least one of the land fingers, with at least one of the connection pads being positioned over and electrically connected to at least one of the lead fingers;
a package body at least partially encapsulating the substrate and the semiconductor chip such that the bottom lead surfaces of the lead fingers are each exposed in a bottom surface of the body.
16. The semiconductor package of claim 15 wherein at least one of the lead fingers is connected to the land.
17. The semiconductor package of claim 15 wherein at least one of the connection pads is positioned over and electrically connected to at least one of the land fingers.
18. The semiconductor package of claim 15 wherein at least one of the connection pads is positioned over and in thermal communication with at least one of the land fingers.
19. The semiconductor package of claim 15 wherein at least some of the lead fingers and at least one of the land fingers each define an angled portion.
20. The semiconductor package of claim 15 wherein each of the lead fingers and the land are formed to include a recessed shoulder therein for enhancing the mechanical interlock thereof to the package body.
21. The semiconductor package of claim 15 wherein:
each of the lead fingers defines an outer end; and
the package body is configured such that the outer end of each of the lead fingers is exposed in a respective one of multiple side surfaces defined by the body.
22. A semiconductor package, comprising:
a substrate comprising a plurality of lead fingers, each of the lead fingers defining opposed top and bottom lead surfaces;
a semiconductor chip comprising:
an active surface; and
a plurality of connection pads disposed on the active surface;
at least one of the connection pads being positioned over and electrically connected to at least one of the lead fingers;
a package body at least partially encapsulating the substrate and the semiconductor chip such that the bottom lead surfaces of the lead fingers are each exposed in a bottom surface of the body, each of the lead fingers being formed to include a recessed shoulder therein for enhancing the mechanical interlock thereof to the package body.