Method for making an integrated circuit substrate having embedded passive components

1. A method of forming a passive component within at least one insulating layer of a semiconductor integrated circuit substrate, the method comprising:

forming an aperture within the at least one insulating layer, the aperture having a bottom above a bottom of the substrate;

laser-activating only the bottom of the aperture;

electroless-plating the bottom of the aperture;

depositing a paste within the aperture to form a body of the passive component; and

plating a top surface of the body to complete the passive component.

2. The method of claim 1 , further comprising depositing a pre-preg layer over the insulating layer and the body of the passive component.

3. The method of claim 2 , further comprising:

forming channels within the pre-preg layer;

depositing conductive material within the channels to form a plurality of conductive patterns; and

forming vias through to the passive component from the plurality of conductive patterns.

4. The method of claim 3 , wherein the forming channels is performed by laser-ablating the channels.

5. The method of claim 3 , wherein the forming channels is performed by embossing the channels.

6. The method of claim 2 , further comprising:

forming one or more apertures within the pre-preg layer; and

applying a resistive paste within the one or more apertures to form a plurality of resistors.

7. The method of claim 1 , wherein the forming an aperture is performed by laser-ablating the aperture.

8. The method of claim 1 , wherein the forming an aperture is performed by embossing the aperture.

9. The method of claim 1 further comprising:

applying a pre-preg layer to a top surface of the substrate;

forming apertures within the pre-preg layer;

depositing a resistive paste within the apertures to form bodies of a plurality of resistors;

forming channels in the prepreg layer abutting the resistor bodies; and

applying conductive material within the channels to form electrical connections to the resistors.

10. A method of forming a capacitor within at least one insulating layer of a semiconductor integrated circuit substrate, the method comprising:

forming an aperture within the at least one insulating layer;

plating a bottom of the aperture to form a first plate of the capacitor; and

depositing a dielectric paste within the aperture to form a body of the capacitor, wherein the insulating layer is a doped insulating layer, and wherein the method further comprises activating the bottom of the aperture exclusive of side walls of the aperture, and wherein the plating is performed via an electro-less plating that deposits metal on the activated bottom of the aperture exclusive of the side walls.

11. The method of claim 10 , wherein the dielectric paste is a doped dielectric paste, and wherein the method further comprises:

activating a top of the dielectric paste; and

plating the activated top of the dielectric paste with an electro-less plating process.

12. The method of claim 11 , wherein the activating a top is performed by exposing the top of the dielectric paste to laser radiation.

13. The method of claim 10 , wherein the activating is performed by exposing the bottom of the aperture to laser radiation.

14. The method of claim 10 , further comprising planarizing a top of the paste-formed body of the capacitor.

15. A method of forming a capacitor within at least one insulating layer of a semiconductor integrated circuit substrate, the method comprising:

forming an aperture within the at least one insulating layer;

plating a bottom of the aperture to form a first plate of the capacitor;

depositing a dielectric paste within the aperture to form a body of the capacitor;

laser ablating the dielectric paste to planarize the dielectric paste at a level beneath a top surface of the insulating layer; and

plating the top of the dielectric paste to form a second plate of the capacitor.

16. The method of claim 15 , further comprising applying a pre-preg material to fill the aperture above the level of the second plate of the capacitor to completely embed the capacitor.

17. The method of claim 15 , further comprising:

applying a second dielectric paste above the second plate of the capacitor to form a second capacitor body; and

plating a top surface of the second capacitor body to form a second capacitor, wherein the plating on the top surface of the second capacitor body forms a second plate of the second capacitor, and wherein the second plate of the capacitor is a first plate of the second capacitor.

18. The method of claim 17 , further comprising electrically connecting the first plate of the capacitor to the second plate of the second capacitor, whereby the capacitor and the second capacitor are connected in parallel to increase a possible capacitance for a given surface area of the aperture.

19. A method of forming a substrate for a semiconductor package, the substrate having embedded passive components, the method comprising:

forming apertures within at least one insulating layer of the substrate, the apertures having bottoms above a bottom of the substrate;

laser-activating only the bottoms of the apertures;

electroless-plating the bottoms of the apertures;

depositing a paste within the apertures to form bodies of a plurality of capacitors; and

plating top surfaces of the bodies to complete the capacitors.