Semiconductor device having insulating and interconnection layers
View Patent ↗A semiconductor device for use in a printed circuit board is provided. In the semiconductor device, metal pillars are disposed perpendicular to bond pads of a semiconductor die. This configuration eliminates the need to form via holes for the connection of interconnection layers and the bond pads of the semiconductor die, thus simplifying the fabrication procedure of the semiconductor device. In addition, the semiconductor die is embedded in the semiconductor device. Based on this configuration, the use of the semiconductor device in a printed circuit board facilitates the stacking of a plurality of semiconductor dies and can reduce the thickness required for the stack, which make the semiconductor device light in weight and small in thickness and size.
1. A semiconductor device comprising:
a semiconductor die having a plurality of bond pads;
pillars disposed perpendicular to and electrically connected to the bond pads;
an integral first insulating layer surrounding and directly contacting and covering the entire semiconductor die including an inactive surface, sides, and an active surface of the semiconductor die, the first insulating layer filling gaps between the pillars;
an inner interconnection layer surrounding the first insulating layer and electrically connected to the pillars, the inner interconnection layer comprising:
a first interconnection layer formed directly on an upper side of the first insulating layer; and
a second interconnection layer formed directly on a lower side of the first insulating layer;
a second insulating layer surrounding the first insulating layer and the inner interconnection layer;
an outer interconnection layer formed directly on the second insulating layer, the outer interconnection layer penetrating the second insulating layer to directly contact and be electrically connected to the inner interconnection layer;
an outer insulating layer surrounding the outer interconnection layer, wherein exposed portions of the outer interconnection layer and exposed portions of the second insulating layer are exposed from the outer insulating layer; and
a bonding metal layer formed on the exposed portions of the outer interconnection layer, the bonding metal layer directly contacting the exposed portions of the second insulating layer.
2. The semiconductor device of claim 1 , further comprising an intermediate layer formed between the pillars and the inner interconnection layer, the intermediate layer being selected from the group consisting of a solder intermediate layer and a tin intermediate layer.
3. The semiconductor device of claim 1 wherein a number of the pillars is the same as a number of the bond pads.
4. The semiconductor device of claim 1 , further comprising a via hole penetrating the first insulating layer.
5. The semiconductor device of claim 4 , wherein the inner interconnection layer extends along an inner wall of the via hole.
6. The semiconductor device of claim 4 , wherein the via hole is filled with the second insulating layer.
7. The semiconductor device of claim 1 , further comprising:
a via hole penetrating the first insulating layer, wherein the inner interconnection layer further comprises:
a third interconnection layer formed along an inner wall of the via hole, the third interconnection layer interconnecting the first interconnection layer with the second interconnection layer.
8. The semiconductor device of claim 1 , wherein the bonding metal layer is selected from the group consisting of a nickel/gold layer and a nickel/palladium/gold layer.
9. A semiconductor device comprising:
a semiconductor die having a plurality of bond pads;
pillars disposed perpendicular to and electrically connected to the bond pads;
an integral first insulating layer surrounding and directly contacting and covering the entire semiconductor die including an inactive surface, sides, and an active surface of the semiconductor die, the first insulating layer filling gaps between the pillars;
an inner interconnection layer embedded into the first insulating layer and electrically connected to the pillars, the inner interconnection layer comprising:
a first interconnection layer embedded into an upper side of the first insulating layer; and
a second interconnection layer embedded into a lower side of the first insulating layer;
a second insulating layer surrounding the first insulating layer and the inner interconnection layer;
an outer interconnection layer formed directly on the second insulating layer, the outer interconnection layer penetrating the second insulating layer to directly contact and be electrically connected to the inner interconnection layer;
an outer insulating layer surrounding the outer interconnection layer, wherein exposed portions of the outer interconnection layer and exposed portions of the second insulating layer are exposed from the outer insulating layer; and
a bonding metal layer formed on the exposed portions of the outer interconnection layer, the bonding metal layer directly contacting the exposed portions of the second insulating layer.
10. The semiconductor device of claim 9 , further comprising an intermediate layer formed between the pillars and the inner interconnection layer, the intermediate layer being selected from the group consisting of a solder intermediate layer and a tin intermediate layer.
11. The semiconductor device of claim 9 wherein a number of the pillars is the same as a number of the bond pads.
12. The semiconductor device of claim 9 , further comprising a via hole penetrating the first insulating layer and the second insulating layer.
13. The semiconductor device of claim 12 , wherein the outer interconnection layer extends along an inner wall of the via hole.
14. The semiconductor device of claim 13 , wherein the via hole is filled with the outer insulating layer.
15. The semiconductor device of claim 12 , wherein the outer interconnection layer comprises:
a first interconnection layer formed on an upper side of the second insulating layer;
a second interconnection layer formed on a lower side of the second insulating layer; and
a third interconnection layer formed along an inner wall of the via hole, the third interconnection layer interconnecting the first interconnection layer of the outer interconnection layer with the second interconnection layer of the outer interconnection layer.
16. A semiconductor device comprising:
a semiconductor die comprising bond pads;
pillars coupled to the bond pads;
an integral first insulating layer directly contacting and covering the entire semiconductor die including an inactive surface, sides, and an active surface of the semiconductor die, the first insulating layer being coupled to the pillars;
an inner interconnection layer coupled to the first insulating layer and the pillars, the inner interconnection layer comprising:
a first interconnection layer directly on an upper side of the first insulating layer; and
a second interconnection layer directly on a lower side of the first insulating layer;
a second insulating layer coupled to the first insulating layer and the inner interconnection layer;
an outer interconnection layer directly on the second insulating layer, the outer interconnection layer penetrating the second insulating layer to directly contact and be electrically connected to the inner interconnection layer;
an outer insulating layer coupled to the outer interconnection layer, wherein exposed portions of the outer interconnection layer and exposed portions of the second insulating layer are exposed from the outer insulating layer; and
a bonding metal layer formed on the exposed portions of the outer interconnection layer, the bonding metal layer directly contacting the exposed portions of the second insulating layer.