IP Library Granted Patent US 8,119,455
Granted Patent B1
US 8,119,455 · App. 13/065,296 · Granted Feb 21, 2012

Wafer level package fabrication method

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Quick Facts
Patent No.
US 8,119,455
App. No.
13/065,296
Granted
Feb 21, 2012
Kind
B1
Abstract

A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric strip to expose the bond pads; and filling the first via apertures with an electrically conductive material to form first vias electrically coupled to the bond pads. The bond pads are directly connected to the corresponding first vias without the use of a solder and without the need to form a solder wetting layer on the bond pads.

Claims (43)

1. A method comprising:

forming an assembly, the assembly comprising:

an electronic component comprising a first surface comprising a bond pad thereon;

an encapsulant encapsulating the entire electronic component except the first surface of the electronic component; and

a first dielectric strip comprising a first surface coupled to the first surface of the electronic component;

forming a first via aperture through the first dielectric strip to expose the bond pad; and

forming a first via by completely covering the bond pad exposed through the first via aperture with an electrically conductive material.

2. The method of claim 1 wherein the encapsulant provides rigidity and support for the assembly.

3. The method of claim 1 further comprising forming a trace electrically coupled to the first via.

4. The method of claim 3 wherein the trace is on a second surface of the first dielectric strip.

5. The method of claim 3 wherein the forming a first via and the forming a trace are performed at the same time.

6. The method of claim 3 wherein the forming a first via and the forming a trace are performed using a single plating operation.

7. The method of claim 3 wherein the trace is in a fan-in configuration.

8. The method of claim 3 wherein the trace is in a fan-out configuration.

9. The method of claim 1 further comprising coupling a second dielectric strip to the first dielectric strip.

10. A method comprising:

forming an assembly, the assembly comprising:

an electronic component comprising a first surface comprising a bond pad thereon;

an encapsulant encapsulating the electronic component; and

a first dielectric strip comprising a first surface coupled to the first surface of the electronic component with an adhesive;

forming a first via aperture through the first dielectric strip to expose the bond pad; and

forming a first via by completely covering the bond pad exposed through the first via aperture with an electrically conductive material.

11. A method comprising:

forming an assembly, the assembly comprising:

an electronic component comprising a first surface comprising bond pads thereon;

an encapsulant encapsulating the electronic component; and

a first dielectric strip comprising a first surface coupled to the first surface of the electronic component;

forming first via apertures through the first dielectric strip to expose the bond pads; and

forming first vias electrically coupled to the bond pads, the first vias completely filling the first via apertures except that the first vias are recessed below a second surface of the first dielectric strip.

12. The method of claim 11 wherein the encapsulant provides rigidity and support for the assembly.

13. The method of claim 11 wherein the encapsulant encapsulates the entire electronic component except the first surface of the electronic component.

14. The method of claim 11 further comprising forming traces electrically coupled to the first vias.

15. The method of claim 14 wherein the traces are on a second surface of the first dielectric strip.

16. The method of claim 14 wherein the forming first vias and the forming traces are performed at the same time.

17. The method of claim 14 wherein the traces are in a fan-in configuration and a fan-out configuration.

18. A method comprising:

forming an assembly, the assembly comprising:

electronic components comprising first surfaces comprising bond pads thereon;

an encapsulant encapsulating the entire electronic components except the first surfaces of the electronic components; and

a first dielectric strip comprising a first surface coupled to the first surfaces of the electronic components;

forming first via apertures through the first dielectric strip to expose the bond pads; and

completely covering the bond pads exposed through the first via apertures with an electrically conductive material to form first vias.

19. The method of claim 18 further comprising forming traces electrically coupled to the first vias, the traces being on a second surface of the first dielectric strip.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2024
From: HUEMOELLER, RONALD PATRICK; RUSLI, SUKIANTO; RAZU, DAVID
To: AMKOR TECHNOLOGY, INC.
Reel/Frame 066078/0770 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2020
From: AMKOR TECHNOLOGY, INC.
To: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE.LTD.
Reel/Frame 054067/0135 →
SECURITY INTEREST Recorded Aug 1, 2018
From: AMKOR TECHNOLOGY, INC.
To: BANK OF AMERICA, N.A., AS AGENT
Reel/Frame 046683/0139 →