Embedded die metal etch stop fabrication method and structure
View Patent ↗A method of forming an electronic component package includes forming a patterned dielectric layer comprising circuit pattern artifacts and at least one electronic component opening. An etch stop metal protected circuit pattern is plated with the circuit pattern artifacts. An electronic component is mounted in the electronic component opening. The etch stop metal protected circuit pattern provide an etch stop for substrate formation etch processes. In this manner, etching of a patterned conductor layer is avoided insuring that impedance is controlled to within tight tolerance.
1. A method of forming an electronic component package comprising:
patterning a first dielectric layer on a first carrier to form a first patterned dielectric layer, the first patterned dielectric layer comprising circuit pattern artifacts and at least one electronic component opening;
plating a first patterned etch stop layer on the first carrier and within the circuit pattern artifacts;
plating a first patterned conductor layer on the first patterned etch stop layer and within the circuit pattern artifacts, wherein the first patterned etch stop layer and the first patterned conductor layer form a first etch stop metal protected circuit pattern, wherein an etch stop metal of the first patterned etch stop layer is selectively etchable compared to a conductor metal of the first patterned conductor layer; and
mounting an active surface comprising bond pads of an electronic component to the first carrier in the electronic component opening with a die attach adhesive, the entire active surface being within the electronic component opening.
2. The method of claim 1 wherein the etch stop metal is selected from the group consisting of nickel, tin, gold, and palladium.
3. The method of claim 1 wherein the conductor metal is selected from the group consisting of copper; silver, and solder.
4. The method of claim 3 wherein the etch stop metal is selected from the group consisting of nickel, tin, gold, and palladium.
5. The method of claim 1 further comprising laminating the first etch stop metal protected circuit pattern to a second carrier with a dielectric material.
6. The method of claim 5 wherein during the laminating, the dielectric material flows to encapsulate the electronic component.
7. The method of claim 5 further comprising removing the first carrier.
8. The method of claim 7 further comprising forming via apertures through the dielectric material and to the second carrier.
9. The method of claim 8 further comprising removing the second carrier.
10. The method of claim 9 wherein the first etch stop metal protected circuit pattern is laminated to a first surface of the dielectric material, the method further comprising forming a circuit pattern on a second surface of the dielectric material.
11. The method of claim 10 further comprising removing the die attach material above the bond pads of the electronic component.
12. The method of claim 11 further comprising etch removing at least a portion of the first patterned etch stop layer.
13. The method of claim 11 further comprising applying a wirebond promoter to the first patterned conductor layer.
14. The method of claim 11 further comprising forming interconnection balls electrically connected to the first patterned conductor layer.
15. The method of claim 11 further comprising electrically connecting the bond pads to the first patterned conductor layer with bond wires.