Semiconductor package having a heat spreader with an exposed exterion surface and a top mold gate
View Patent ↗A semiconductor device has a substrate. A die is attached to a first surface of the substrate. A heat sink is provided having an approximately planer member and support members extending from the planer member. The support members are attached to the first surface of the substrate to form a cavity over the die with the planer member positioned above the die. An encapsulant is provided for encapsulating the device, wherein an exterior surface of the planer member is exposed. A non-tapered opening is formed in the planer member. The encapsulant is injected through the opening to encapsulate the cavity and the encapsulant will partially fill the non-tapered opening.
1. A semiconductor device comprising:
a substrate;
a die attached to a first surface of the substrate;
a heat sink having an approximately planer member and support members extending from the planer member, the support members attached to the first surface of the substrate to form a cavity over the die with the planer member positioned above the die;
an encapsulant for encapsulating the device, wherein an entire exterior surface of the planer member is exposed; and
a non-tapered opening formed in the planer member, the encapsulant injected through the opening to encapsulate the cavity, the encapsulant partially filling the non-tapered opening.
2. The semiconductor device in accordance with claim 1 further comprising:
a filler die having a first surface attached to the interior surface of the planer member and a second surface attached to a first surface of the die; and
at least one channel formed in the first surface of the filler die, the channel aligned with the non-tapered opening.
3. The semiconductor device in accordance with claim 2 further comprising a thermal interface material applied between the first surface of the filler die and the interior surface of the planer member and between the second surface of the filler die and the first surface of the die.
4. The semiconductor device in accordance with claim 2 further comprising a plurality of channels formed in the first surface of the filler die, the plurality of channels having an intersection, the intersection aligned with the non-tapered opening.
5. The semiconductor device in accordance with claim 2 wherein the filler die has an approximately equal Coefficient of Thermal Expansion (CTE) as the die.
6. The semiconductor device in accordance with claim 1 further comprising a plurality of contacts coupled to a second surface of the substrate.
7. The semiconductor device in accordance with claim 2 further comprising a plurality of contacts coupled to a second surface of the substrate.
8. The semiconductor device in accordance with claim 1 further comprising a plurality of filler dies having first surfaces attached to the interior surface of the planer member and second surfaces attached to a first surface of the die, the plurality of filler dies positioned on the first surface of the die to form at least one pathway in the first surface of the die, the pathway aligned with the non-tapered opening.
9. The semiconductor device in accordance with claim 8 further comprising a thermal interface material applied between the first surfaces of the filler dies and the interior surface of the planer member and between the second surfaces of the filler dies and the first surface of the die.
10. The semiconductor device in accordance with claim 1 further comprising a plurality of filler dies having first surface attached to the interior surface of the planer member and second surfaces attached to a first surface of the die, the plurality of filler dies positioned on the first surface of the die to form a plurality of pathway in the first surface of the die, the plurality of pathways having an intersection, the intersection of the pathways aligned with the non-tapered opening.
11. The semiconductor device in accordance with claim 8 further comprising a plurality of contacts coupled to a second surface of the substrate.
12. A semiconductor device comprising:
a substrate;
a die attached to a first surface of the substrate;
a heat sink having an approximately planer member and support members extending from the planer member, the support members attached to the first surface of the substrate to form a cavity over the die with the planer member positioned above the die;
an encapsulant for encapsulating the device, wherein an exterior surface of the planer member is exposed;
means formed in the planer member for injecting the encapsulant into the cavity, the encapsulant partially filling the means;
a filler die having a first surface attached to the interior surface of the planer member and a second surface attached to a first surface of the die; and
means formed in the first surface of the filler die for allowing the encapsulant to flow across the first surface of filler die, the means formed in the first surface of the filler die aligned with the means formed in the planer member.
13. The semiconductor device in accordance with claim 12 further comprising means placed between the second surface of the filler die and the first surface of the die and the first surface of the filler die and the interior surface of the planer member to increase thermal transfer efficiency.
14. The semiconductor device in accordance with claim 12 further comprising a plurality of filler dies having first surfaces attached to the interior surface of the planer member and second surfaces attached to a first surface of the die, the plurality of filler dies positioned on the first surface of the die to form at least one pathway in the first surface of the die, the pathway aligned with the means formed in the planer member.
15. The semiconductor device in accordance with claim 14 further comprising means applied between the first surfaces of the filler dies and the interior surface of the planer member and between the second surfaces of the filler dies and the first surface of the die to increase thermal transfer efficiency.
16. A semiconductor device comprising:
a substrate;
a die attached to a first surface of the substrate;
a heat sink positioned over the die and attached to the first surface of the substrate to form a cavity over the die;
an encapsulant for encapsulating the device, wherein an exterior surface of the planer member is exposed;
a non-tapered opening formed in the planer member, the encapsulant injected through the opening to encapsulate the cavity, the encapsulant partially filling the non-tapered opening;
a filler die having a first surface attached to an interior surface of the heat sink and a second surface attached to a first surface of the die; and
at least one channel formed in the first surface of the filler die, the channel aligned with the non-tapered opening.
17. The semiconductor device in accordance with claim 16 further comprising a plurality of channels formed in the first surface of the filler die, the plurality of channels having an intersection, the intersection aligned with the non-tapered opening.
18. The semiconductor device in accordance with claim 16 further comprising a plurality of filler dies having first surfaces attached to the interior surface of the planer member and second surfaces attached to a first surface of the die, the plurality of filler dies positioned on the first surface of the die to form at least one pathway in the first surface of the die, the pathway aligned with the non-tapered opening.