Two-sided wafer escape package

1. An electronic component package comprising:

an electronic component comprising:

a first surface comprising bond pads;

a second surface opposite the first surface; and

sides extending between the first surface and the second surface;

a lower dielectric strip comprising a first surface coupled to the first surface of the electronic component;

an upper dielectric strip comprising a first surface coupled to the second surface of the electronic component;

lower vias extending through the lower dielectric strip and being coupled to the bond pads; and

upper vias extending through the upper dielectric strip and being coupled to bonding locations on the second surface of the electronic component, the bonding location being coupled to the bond pads.

2. The electronic component package of claim 1 , further comprising:

trace channels in the upper or lower dielectric layer.

3. The electronic component package of claim 2 , wherein the trace channels are trapezoidal trace channels.

4. The electronic component package of claim 2 further comprising:

a metal layer applied to an inner surface of at least one of said trace channels to form at least one electrically conductive trace.

5. An electronic component package comprising:

an electronic component comprising a first surface comprising bond pads;

a lower dielectric strip comprising a first surface coupled to the first surface of the electronic component, wherein the first surface of the lower dielectric strip is coupled to the first surface of the electronic component with an adhesive;

an upper dielectric strip comprising a first surface coupled to a second surface of the electronic component;

lower vias extending through the lower dielectric strip and being coupled to the bond pads;

upper vias extending through the upper dielectric strip and being coupled to bonding locations on the second surface of the electronic component, the bonding location being coupled to the bond pads.

6. An electronic component package comprising:

an electronic component comprising a first surface comprising bond pads;

a lower dielectric strip comprising a first surface coupled to the first surface of the electronic component;

an upper dielectric strip comprising a first surface coupled to a second surface of the electronic component, wherein the first surface of the upper dielectric strip is coupled to the second surface of the electronic component with an adhesive;

lower vias extending through the lower dielectric strip and being coupled to the bond pads;

upper vias extending through the upper dielectric strip and being coupled to bonding locations on the second surface of the electronic component, the bonding location being coupled to the bond pads.

7. An electronic component package comprising:

an electronic component comprising a first surface comprising bond pads;

a lower dielectric strip comprising a first surface coupled to the first surface of the electronic component;

a first adhesive coupling the first surface of the lower dielectric strip to the first surface of the electronic component;

an upper dielectric strip comprising a first surface coupled to a second surface of the electronic component;

a second adhesive coupling the first surface of the upper dielectric strip to the second surface of the electronic component;

lower vias extending through the lower dielectric strip and being coupled to the bond pads;

upper vias extending through the upper dielectric strip and being coupled to bonding locations on the second surface of the electronic component, the bonding location being coupled to the bond pads.

8. An electronic component package comprising:

an electronic component having a plurality of bond pads formed on a first surface of the electronic component;

electrically conductive traces connecting first selected bond pads of the plurality of bond pads on the first surface of the electronic component to corresponding bonding locations on a second surface of the electronic component;

a lower dielectric strip comprising a first surface coupled to the first surface of the electronic component;

an upper dielectric strip comprising a first surface coupled the second surface of the electronic component;

lower via apertures through the lower dielectric strip to expose second selected bond pads of the plurality of bond pads on the first surface of the electronic component;

upper via apertures through the upper dielectric strip to expose the bonding locations on the second surface of the electronic component;

lower vias electrically coupled to the second selected bond pads of the plurality of bond pads on the first surface of the electronic component, the lower vias comprising an electrically conductive material filling the lower via apertures; and

upper vias electrically coupled to the bonding locations on the second surface of the electronic component, the upper vias comprising an electrically conductive material filling the upper via apertures.

9. The electronic component package of claim 8 , further comprising:

trace channels in the upper or lower dielectric layer.

10. The electronic component package of claim 9 , wherein the trace channels comprise roughened texture on sides of the trace channels.

11. The electronic component package of claim 10 further comprising:

at least one electrically conductive trace comprising a metal layer applied to an inner surface of at least one of the trace channels.

12. The electronic component package of claim 8 wherein the lower vias extend from the bond pads through the lower dielectric strip to be adjacent a second surface of the lower dielectric strip.

13. The electronic component package of claim 8 wherein the upper vias extend from the bonding locations through the upper dielectric strip to be adjacent a second surface of the upper dielectric strip.

14. The electronic component package of claim 8 wherein the lower vias extend from the bond pads through the lower dielectric strip to be recessed from a second surface of the lower dielectric strip.

15. The electronic component package of claim 8 wherein the upper vias extend from the bonding locations through the upper dielectric strip to be recessed from a second surface of the upper dielectric strip.

16. The electronic component package of claim 8 further comprising an adhesive coupling the first surface of the electronic component to the first surface of the lower dielectric strip.

17. The electronic component package of claim 8 further comprising an adhesive coupling the second surface of the electronic component to the first surface of the upper dielectric strip.

18. An electronic component package comprising:

an electronic component, the electronic component having a plurality of bond pads formed on a first surface of the electronic component;

electrically conductive traces connecting first selected bond pads of the plurality of bond pads on the first surface of the electronic component to corresponding bonding locations on a second surface of the electronic component;

a first adhesive coupling the first surface of the electronic component to a first surface of a lower dielectric strip;

a second adhesive coupling the second surface of the electronic component to a first surface of an upper dielectric strip;

lower via apertures through the lower dielectric strip and the first adhesive to expose second selected bond pads of the plurality of bond pads on the first surface of the electronic component;

upper via apertures through the upper dielectric strip and the second adhesive to expose the bonding locations on the second surface of the electronic component;

lower vias electrically coupled to the second selected bond pads of the plurality of bond pads on the first surface of the electronic component; and

upper vias electrically coupled to the bonding locations on the second surface of the electronic component.

19. The electronic component package of claim 18 wherein the lower via apertures are formed by laser ablation.

20. The electronic component package of claim 18 wherein the upper via apertures are formed by laser ablation.