Error correcting latch
View Patent ↗An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass gate, an output for providing a data output signal, and a control node for receiving the control signal, an inverter having an input coupled to the output of the first pass gate and an output; and a correcting inverter stage having a first input coupled to the output of the inverter, and second and third inputs for receiving voting signals from adjacent error-correcting latch stages, and an output coupled to the output of the second pass gate. A full latch stage includes three interconnected partial latch stages. The full latch stage has a high degree of immunity from SEU events and from on-chip noise coupling.
1. An error-correcting latch comprising:
first, second, and third error-correcting latch stages each including a clock input; and
first, second, and third clock signal buses respectively coupled to the clock input of the first, second, and third error-correcting latch stages through a first, second, and third driver circuit, and
wherein each latch stage further comprises a two-of-three voting circuit placed in a feedback loop of the latch stage.
2. The error-correcting latch as in claim 1 wherein a same clock signal is provided on the first, second, and third clock signal buses.
3. The error-correcting latch as in claim 1 wherein the first, second, and third clock signal buses are respectively coupled to first, second, and third bonding pads.
4. The error-correcting latch as in claim 1 wherein the first, second, and third driver circuits are driven by a common fourth driver circuit.
5. The error-correcting latch as in claim 1 further comprising at least one additional error-correcting commonly latch coupled to the first, second, and third clock signal buses.
6. An error-correcting latch comprising:
first, second, and third error-correcting latch stages each including a data input; and
first, second, and third data signal buses respectively coupled to the data input of the first, second, and third error-correcting latch stages through a first, second, and third driver circuit, and
wherein each latch stage further comprises a two-of-three voting circuit placed in a feedback loop of the latch stage.
7. The error-correcting latch as in claim 6 wherein a same data signal is provided on the first, second, and third data signal buses.
8. The error-correcting latch as in claim 6 wherein the first, second, and third data signal buses are respectively coupled to first, second, and third bonding pads.
9. The error-correcting latch as in claim 6 wherein the first, second, and third driver circuits are driven by a common fourth driver circuit.
10. The error-correcting latch as in claim 6 further comprising at least one additional error-correcting latch commonly coupled to the first, second, and third data signal buses.
11. An error-correcting latch comprising:
first, second, and third error-correcting latch stages each including at least two control signal inputs; and
first and second control signal buses respectively coupled to the control signal inputs of the first, second, and third error-correcting latch stages, and
wherein each latch stage further comprises a two-of-three voting circuit placed in a feedback loop of the latch stage.
12. The error-correcting latch as in claim 11 wherein a same control signal is provided on the first and second control signal buses.
13. The error-correcting latch as in claim 11 wherein the first and second control signal buses are respectively coupled to first and second bonding pads.
14. The error-correcting latch as in claim 11 further comprising at least one additional error-correcting latch commonly coupled to the first and second control signal buses.
15. The error-correcting latch stage as in claim 11 in which the control signal buses each comprise a preset signal bus.
16. The error-correcting latch stage as in claim 11 in which the control signal buses each comprise a clear signal bus.
17. The error-correcting latch stage as in claim 11 in which the control signal buses each comprise a set signal bus.
18. The error-correcting latch stage as in claim 11 in which the control signal buses each comprise a reset signal bus.
19. The error-correcting latch as in claim 11 wherein the first and second control signal buses are coupled to the control signal inputs of the first, second, and third error-correcting latch stages through first and second driver circuits.
20. The error-correcting latch as in claim 19 wherein the first and second driver circuits are driven by a common third driver circuit.