Method for making a three-dimensional integrated circuit structure
View Patent ↗Vertically oriented semiconductor devices may be added to a separately fabricated substrate that includes electrical devices and/or interconnect. The plurality of vertically oriented semiconductor devices are physically separated from each other, and are not disposed within the same semiconductor body, or semiconductor substrate. The plurality of vertically oriented semiconductor devices may be added to the separately fabricated substrate as a thin layer including several doped semiconductor regions which, subsequent to attachment, are etched to produce individual doped stack structures. Alternatively, the plurality of vertically oriented semiconductor devices may be fabricated prior to attachment to the separately fabricated substrate. The doped stack structures may form the basis for diodes, capacitors, n-MOSFETs, p-MOSFETs, bipolar transistors, and floating gate transistors. Ferroelectric memory devices, Ferromagnetic memory devices, chalcogenide phase change devices, may be formed in a stackable add-on layer for use in conjunction with a separately fabricated substrate. Stackable add-on layers may include interconnect lines.
1. A method of forming a semiconductor structure, comprising:
providing a substrate having electrical devices formed therein, and further having at least one dielectric layer and at least one interconnect layer disposed above the substrate;
providing a first stackable add-on layer, the first stackable add-on layer including a plurality of vertically oriented semiconductor devices disposed within the first stackable add-on layer, the plurality of vertically oriented semiconductor devices separated from each other by dielectric material; and
attaching the stackable add-on layer to a layer of the substrate that is the greatest distance from the substrate as measured from the bottom surface of the substrate.
2. The method of claim 1 , wherein the plurality of vertically oriented semiconductor devices includes at least one n-p-n stack.
3. The method of claim 2 , further comprising forming a gate dielectric on the n-p-n stack, and forming a gate electrode on the gate dielectric.
4. The method of claim 3 , wherein the gate electrode is disposed on the gate dielectric such that it is adjacent at least a p region of the n-p-n stack so as to form an n-type MOSFET.
5. The method of claim 1 , wherein the plurality of vertically oriented semiconductor devices includes at least one p-n-p stack.
6. The method of claim 5 , further comprising forming a gate dielectric on the p-n-p stack, and forming a gate electrode on the gate dielectric.
7. The method of claim 6 , wherein the gate electrode is disposed on the gate dielectric such that it is adjacent at least an n region of the p-n-p stack so as to form a p-type MOSFET.
8. The method of claim 1 , wherein the plurality of vertically oriented semiconductor devices includes at least one floating gate non-volatile memory device.
9. The method of claim 8 , wherein a vertically oriented erase gate is disposed adjacent the at least one floating gate non-volatile memory device.
10. The method of claim 1 , further comprising attaching a second stackable add-on layer above the first stackable add-on layer.