Synchronization between low frequency and high frequency digital signals
View Patent ↗A synchronization circuit for synchronizing low frequency digital circuitry and high frequency digital circuitry. The synchronization circuit produces an ordered series of clocks from the high-frequency digital clock. The clocks have a deterministic time relationship, with at least one clock having a period longer than the timing uncertainty associated with a synchronization signal. The synchronization signal is passed through a chain of latches, each one clocked by one of the divided down clocks with successively higher frequency. These latches align the synchronization signal with the clocks produced by the clock divider, ultimately aligning the synchronization signal with the high frequency clock. This synchronization circuit is described in connection with automatic test equipment used in the manufacture of semiconductor devices.
1. Circuitry comprising:
a) a first sub-circuit clocked with a first clock and having an output;
b) a second sub-circuit, clocked with a second clock having a frequency greater than the first clock, the second sub-circuit having an input;
c) a synchronization circuit having an input coupled to the output of the first sub-circuit and an output coupled to the input of the second sub-circuit and a clock input coupled to the second clock, the synchronization circuit comprising:
i) a clock divider producing a plurality of ordered clocks synchronized relative to the second clock, the plurality of ordered clocks having an order such that each clock has a longer period than the clock prior to it in the order;
ii) a chain of latches having a data input and a data output and a plurality of clock inputs, each clock input coupled to a clock of the plurality of ordered clocks and the data input coupled to the output of the first sub-circuit.
2. The circuitry of claim 1 wherein the second clock is generated by direct digital synthesis.
3. The circuitry of claim 2 wherein the second clock has a frequency in excess of 500 MHz and the first clock has a frequency less than 200 MHz.
4. Automatic test equipment comprising the circuitry of claim 2 wherein the second sub-circuit is a portion of a high frequency AC instrument.
5. The circuitry of claim 1 wherein the clock divider comprises a chain of divider circuits, each divider circuit having an input and an output, with the input of each successive divider circuit in the chain connected to the output of a prior divider circuit in the chain, each divider circuit outputting a clock with half the frequency at its input, with the input of the first divider circuit in the chain coupled to the second clock.
6. The circuitry of claim 1 wherein the clock divider comprises:
a) a chain of divider circuits, each divider circuit having an input and an output, with the input of each successive divider circuit in the chain connected to the output of a prior divider circuit in the chain, each divider circuit outputting a clock with half the frequency at its input, with the input of the first divider circuit in the chain coupled to the second clock.
7. The circuitry of claim 6 wherein each of the divider circuits comprises a D-type flip-flop.
8. Circuitry comprising:
a) a first sub-circuit clocked with a first clock and producing an output;
b) a second sub-circuit, clocked with a second clock, the second sub-circuit having an input;
c) a synchronization circuit comprising:
i) clock divider circuitry providing a plurality of ordered clocks synchronized relative to the second clock, the plurality of ordered clocks having an order such that each clock has a longer period than the clock prior to it in the order;
ii) a plurality of latches, each latch having a data input and a data output and a clock input, wherein:
A) the plurality of latches having an order with the clock input of each latch coupled to one of the plurality of ordered clocks with each of the plurality of latches and the ordered clock coupled thereto having the same relative position in their respective orders;
B) the data input of the last latch in the order is coupled to the output of the first sub-circuit and a data input of every other latch in the order is coupled to the data output of the next latch in the order; and
C) the data output of the first latch in the order is coupled to the input of the second sub-circuit.
9. The circuitry of claim 8 wherein the second clock is generated by direct digital synthesis.
10. The circuitry of claim 9 wherein the second clock has a frequency in excess of 500 MHz and the first clock has a frequency less than 200 MHz.
11. Automatic test equipment comprising the circuitry of claim 9 wherein the second sub-circuit is a portion of a high frequency AC instrument.
12. A method of synchronizing a first sub-circuit, clocked with a first clock, with a second sub-circuit, clocked with a second clock comprising:
a) generating a plurality of clocks from the second clock, individual ones of the plurality of clocks being synchronized with the second clock and having a period different than the period of the second clock;
b) generating a signal for the first sub-circuit, the signal having jitter associated therewith;
c) aligning the signal with one of the plurality of clocks having a period longer than the magnitude of the jitter associated with the signal; and
d) thereafter aligning the signal with the second clock; and
e) synchronizing the second sub-circuit with the signal after it has been aligned with the second clock.
13. The method of synchronizing a first sub-circuit with a second sub-circuit of claim 12 wherein the signal is synchronized to the first clock.
14. A method of manufacturing semiconductor devices employing test equipment having a first sub-circuit and a second sub-circuit, comprising:
a) synchronizing the first sub-circuit and the second sub-circuit in the test equipment according to the method of claim 12 ;
b) generating test signals with at least one of the first sub-circuit and the second sub-circuit and applying the test signals to semiconductor devices during their manufacture;
c) measuring with the test equipment responses to the test signals from the semiconductor devices; and
d) altering the manufacturing operation based on measurements made with the test equipment.
15. The method of synchronizing a first sub-circuit with a second sub-circuit of claim 12 wherein generating a plurality of clocks comprises dividing the second clock.
16. The method of synchronizing a first sub-circuit with a second sub-circuit of claim 12 wherein aligning the signal with one of the plurality of clocks comprises latching the signal in a latch clocked by the one of the plurality of clocks.
17. The method of synchronizing a first sub-circuit with a second sub-circuit of claim 12 wherein aligning the signal with the second clock comprises successively latching the signal in latches clocked by ones of the plurality of clocks.