IP Library Granted Patent US 6,930,001
Granted Patent B2
US 6,930,001 · App. 10/876,065 · Granted Aug 16, 2005

Method for manufacturing NAND flash device

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Quick Facts
Patent No.
US 6,930,001
App. No.
10/876,065
Granted
Aug 16, 2005
Kind
B2
Abstract

Disclosed is a method for manufacturing a NAND flash device. After a source line plug hole is formed, a drain contact plug hole is formed. The holes are filled with a conductive material film and are then polished. It is therefore possible to simplify the process since a blanket etch process step is omitted. Moreover, loss of a drain contact plug by the blanket etch process is prevented. It is therefore possible to improve the electrical properties of a device and reduce the manufacturing cost price.

Claims (14)

1. A method for manufacturing a NAND flash device, comprising the steps of:

providing a semiconductor substrate on which a drain select transistor for selecting a drain terminal of a flash cell and a source select transistor for selecting a source terminal of the flash cell, wherein the drain select transistor and the source select transistor have drain region and a source region on the surface of the semiconductor substrate;

forming a first interlayer insulating film over the semiconductor substrate;

removing a portion of the first interlayer insulating film to form a source line contact hole, wherein the source region of the source select transistor is exposed at the bottom of the source line contact hole;

removing a portion of the first interlayer insulating film to form a drain contact hole, wherein the drain region of the drain select transistor is exposed at the bottom of the drain contact hole;

forming a source line plug and a drain contact plug in the source line contact hole and the drain contact hole, respectively;

forming a second interlayer insulating film over the semiconductor substrate including the source line plug and the drain contact plug;

forming an etch-stop layer on the second interlayer insulating layer;

forming a third interlayer insulating film on etch-stop layer;

selectively etching the third interlayer insulating film, the etch-stop layer and portions of the second interlayer insulating layer and forming a first trench over the drain contact plug and a second trench over the source line plug, wherein the first trench is larger than the second trench;

selectively removing the second interlayer insulating layer and forming a first via hole under the first trench and the second via hole under the second trench, wherein the first via hole exposes the drain contact plug and the second via hole exposes the source line plug;

filling the first trench, the second trench, the first via hole and the second via hole with a metal film; and

forming a bit line passing the first trench and the first via hole and a common source line contact passing the second trench and the second via hole by polishing the metal film.

2. The method of claim 1 , further comprising the step of implanting impurities into the source region and the drain region which are exposed at the bottoms of the source line contact hole and the drain contact hole respectively.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2015
From: NUMONYX B. V.
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 036319/0139 →
CHANGE OF NAME Recorded Aug 10, 2015
From: HYNIX SEMICONDUCTOR INC.
To: SK HYNIX INC.
Reel/Frame 036319/0271 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2006
From: HYNIX SEMICONDUCTOR INC.
To: HYNIX SEMICONDUCTOR INC.; STMICROELECTRONICS S.R.L.
Reel/Frame 018207/0057 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2004
From: GIL, MIN C.
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 015519/0334 →