Comparator feedback peak detector
View Patent ↗There is disclosed a circuit and a process for detecting peak-to-peak voltage. The circuit comprises a first comparator having an output coupled to a first capacitor, a non-inverting input for receiving a high frequency AC waveform, and an inverting input, a second comparator having an output coupled to a second capacitor, and a first second input, an operational amplifier having a non-inverting input coupled to the inverting input of the first comparator, and an inverting input coupled to the first input. The process comprises charging a first capacitor when a high frequency AC waveform voltage is greater than a buffered voltage of the first capacitor, charging a second capacitor when an inverted buffered voltage of the second capacitor is greater than the high frequency AC waveform voltage, and outputting a voltage based on the buffered voltage of the first capacitor and the inverted buffered voltage of the second capacitor.
1. A circuit comprising:
a first capacitor
a first comparator having
an output coupled to the first capacitor
a non-inverting input for receiving a high frequency AC waveform
an inverting input
a second capacitor
a second comparator having
an output coupled to the second capacitor
a first input
a second input
a first buffer amplifier having
an input coupled to the first capacitor
an output coupled to the inverting input of the first comparator
a second buffer amplifier having
an input coupled to the second capacitor
an output
an inverting amplifier having
an input coupled to the output of the second buffer amplifier
an output coupled to the first input of the second comparator
an operational amplifier having
a non-inverting input coupled to the inverting input of the first comparator and the output of the first buffer amplifier
an inverting input coupled to the first input of the second comparator and the output of the inverting amplifier.
2. The circuit of claim 1 , further comprising:
a first high speed diode coupled between the first capacitor and the output of the first comparator
a second high speed diode coupled between the second capacitor and the output of the second comparator.
3. The circuit of claim 2 , wherein:
the first input is an non-inverting input for receiving an inverted buffered voltage of the second capacitor
the second input is an inverting input for receiving the high frequency AC waveform,
the second input is coupled to the non-inverting input of the first comparator.
4. A circuit comprising:
a first capacitor
a first comparator having
an output coupled to the first capacitor
a non-inverting input for receiving a high frequency AC waveform
an inverting input
a second capacitor
a second comparator having
an output coupled to the second capacitor
a first input
a second input
a first high speed diode coupled between the first capacitor and the output of the first comparator
a second high speed diode coupled between the second capacitor and the output of the second comparator
a first buffer amplifier having
an input coupled to the first capacitor
an output coupled to the inverting input of the first comparator
a second buffer amplifier having
an input coupled to the second capacitor
an output
an inverting amplifier having
an input coupled to the output of the second buffer amplifier
an output coupled to the first input
an operational amplifier having
a non-inverting input coupled to the inverting input of the first comparator
an inverting input coupled to the first input
wherein the first input is an non-inverting input for receiving an inverted buffered voltage of the second capacitor
wherein the second input is an inverting input for receiving the high frequency AC waveform
wherein the second input is coupled to the non-inverting input of the first comparator.
5. The circuit of claim 4 , wherein the comparators are high speed comparators.
6. The circuit of claim 4 , further comprising:
for each comparator, an ECL-TTL translator coupled between the comparator and the capacitor, wherein the comparators are ECL comparators.
7. The circuit of claim 4 , further comprising:
a first FET switch coupled between the first capacitor and a sink, the first FET switch for discharging the first capacitor when the first FET switch receives a RESET signal
a second FET switch coupled between the second capacitor and the sink, the second FET switch for discharging the second capacitor when the second FET switch receives the RESET signal.
8. The circuit of claim 2 , wherein:
the first input is an inverting input for receiving a buffered voltage of the second capacitor
the second input is a non-inverting input for receiving an inverted high frequency AC waveform.
9. The circuit of claim 8 , wherein the comparators are high speed comparators.
10. A circuit comprising:
a first capacitor
a first comparator having
an output coupled to the first capacitor
a non-inverting input for receiving a high frequency AC waveform
an inverting input
a second capacitor
a second comparator having
an output coupled to the second capacitor
a first input
a second input
an operational amplifier having
a non-inverting input coupled to the inverting input of the first comparator
an inverting input coupled to the first input
a first high speed diode coupled between the first capacitor and the output of the first comparator
a second high speed diode coupled between the second capacitor and the output of the second comparator
a first buffer amplifier having
an input coupled to the first capacitor
an output coupled to the inverting input of the first comparator
a second buffer amplifier having
an input coupled to the second capacitor
an output coupled to the first input
an inverting amplifier having
an input coupled to tenon-inverting input of the first comparator
an output coupled to the second input
for each comparator, an ECL-TTL translator coupled between the comparator and the capacitor, wherein the comparators are ECL comparators
wherein the first input is an inverting input for receiving a buffered voltage of the second capacitor
wherein the second input is a non-inverting input for receiving an inverted high frequency AC waveform.
11. The circuit of claim 8 , further comprising:
a first FET switch coupled between the first capacitor and a sink, the first FET switch for discharging the first capacitor when the first FET switch receives a RESET signal
a second FET switch coupled between the second capacitor and the sink, the second FET switch for discharging the second capacitor when the second FET switch receives the RESET signal.
12. The circuit of claim 2 , wherein the operational amplifier further comprises an output coupled with a digitizer of an automated testing system.
13. The circuit of claim 11 , further comprising an automated testing system, the automated testing system comprising a digitizer and a capture memory, the digitizer coupled with an output of the operational amplifier, the capture memory coupled with the digitizer, wherein the RESET signal is a periodic pulse having a fixed interval.
14. An automated testing system including the circuit of claim 7 .