Transistor in a semiconductor substrate having high-concentration source and drain region formed at the bottom of a trench adjacent to the gate electrode
View Patent ↗The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. Trenches are formed in a semiconductor substrate at gate edges. Low-concentration impurity regions are then formed at the sidewalls and the bottoms of the trenches. High-concentration impurity regions are formed at the bottoms of the trenches in a depth shallower than the low-concentration impurity regions. Source/drain consisting of the low-concentration impurity regions and the high-concentration impurity regions are thus formed. Therefore, the size of the transistor can be reduced while securing a stabilized operating characteristic even at high voltage. It is thus possible to improve reliability of the circuit and the degree of integration in the device.
1. A transistor in a semiconductor device, comprising:
a well formed by a first conductivity type impurity in an active region of a semiconductor substrate;
a low-concentration impurity region formed by a second conductivity type impurity on the active region;
a gate oxide film and a gate formed over a surface of the semiconductor substrate;
an isolation region formed in the semiconductor substrate;
a trench surrounded by the low-concentration impurity region;
dielectric film spacers formed on both sidewalls of the gate and the trench;
a high-concentration impurity region formed by the second conductivity type impurity at the bottom of the trench and the dielectric film spacers to form source/drain regions; and
a drift junction formed in a portion of a channel region in the well by a same dopant type of impurity as an impurity of the well,
wherein the high-concentration impurity region is formed to have a distance 1.0 μm to 2.0 μm, when the transistor stably operates at substantially 40 V, from a bottom surface of the gate oxide film in a vertical direction.
2. The transistor as claimed in claim 1 , wherein the high-concentration impurity region is formed only at the trench in a self-aligned manner.
3. The transistor as claimed in claim 1 , wherein the trench is formed between the gate and an adjacent isolation region.
4. The transistor as claimed in claim 1 , further comprising:
an interlayer insulating film formed over the semiconductor substrate;
a contact plug formed on each a source/drain through the interlayer insulating film;
a metal wire formed on the interlayer insulating film including the contact plug.
5. The transistor as claimed in claim 1 , wherein a height of a dielectric film spacer formed adjacent the gate is higher than a height of a dielectric film spacer formed adjacent the trench.
6. The transistor as claimed in claim 1 , wherein a size (L VDMOS ) of the transistor is formed to satisfy the following:
L VDMOS =2L DO +L GATE2 , wherein L DO is a width for which the low-concentration impurity region and the gate are overlapped, and L GATE2 is a channel width.
7. The transistor as claimed in claim 1 , wherein the trench has a width narrower than the low-concentration impurity region, and a depth of the trench is shallower than a depth of the low-concentration impurity region.