Multi-port memory device with precharge control

1. A multi-port memory device, comprising:

a global data bus having a plurality of bus lines;

a plurality of data transmission/reception blocks, each of which includes a current sensing type transmitter/receiver for exchanging data with the global data bus, the data transmission/reception block including a plurality of banks and ports;

a plurality of switching units for discharging each bus line of the global data bus in response to an initialization signal; and

an initialization signal generator for generating the initialization signal in response to a bank active information signal defining an active section of all banks, which exchanges data with a corresponding one of the global data bus,

wherein the initialization signal generator includes:

a pulse generation unit for generating a bank active information pulse in response to the bank active information signal;

a section signal generation unit for receiving the bank active information pulse and generating a bank active ignore signal for ignoring an activation of the bank active information pulse for a predetermined time after the bank active information pulse is activated; and

a logic combination unit for generating the initialization signal in response to a power-up signal, the bank active information pulse and the bank active ignore signal.

2. The multi-port memory device as recited in claim 1 , wherein each of the switching units includes an NMOS transistor which is connected between the bus line and the global data bus and has a gate receiving the initialization signal.

3. The multi-port memory device as recited in claim 2 , wherein the initialization signal is applied through one common line with respect to the plurality of switching units.

4. The multi-port memory device as recited in claim 1 , wherein the pulse generation unit includes:

a delay circuit configured to receive the bank active information signal;

a first inverter configured to receive an output of the delay circuit;

a first NAND gate configured to receive an output of the first inverter and the bank active information signal; and

a second inverter configured to receive an output of the first NAND gate and output the bank active information pulse.

5. The multi-port memory device as recited in claim 4 , wherein the section signal generation unit includes:

a second delay circuit configured to receive the bank active information pulse;

a third inverter configured to receive an output of the second delay circuit;

a fourth inverter configured to receive an output of the third inverter and output a delayed bank active information pulse;

a buffer configured with a pull-down NMOS transistor having a gate receiving the delayed bank active information pulse, a pull-down NMOS transistor and a pull-up PMOS transistor, each of which has a gate receiving a period end pulse;

a PMOS transistor for initializing an output terminal of the buffer, the PMOS transistor being connected between the output terminal of the buffer and a power supply voltage terminal and having a gate receiving an inverted power-up signal;

an inverter latch for latching an output of the buffer;

a fifth inverter configured to receive an output of the inverter latch and output the bank active ignore signal;

a ring oscillator configured to receive the output of the inverter latch; and

a sixth inverter configured to receive an output of the ring oscillator and generate the period end pulse.

6. The multi-port memory device as recited in claim 5 , wherein the logic combination unit includes:

a second NAND gate configured to receive the bank active information pulse and the bank active ignore signal;

a seventh inverter configured to receive an output of the second NAND gate;

a NOR gate configured to receive the power-up signal and an output of the seventh inverter; and

an eighth inverter configured to receive an output of the NOR gate and output the initialization signal.

7. A multi-port memory device, comprising:

a global data bus having a plurality of bus lines;

a plurality of data transmission/reception blocks, each of which includes a current sensing type transmitter/receiver for exchanging data with the global data bus, the data transmission/reception block including a plurality of banks and ports;

a plurality of switching units for discharging each bus line of the global data bus in response to an initialization signal; and

an initialization signal generator for generating the initialization signal in response to a bank active information signal defining an active section of all banks, which exchanges data with a corresponding one of the global data bus,

wherein the initialization signal generator includes:

a pulse generation unit for generating a bank active information pulse in response to the bank active information signal;

a pulse processing unit for outputting an initial control signal and an oscillation enable signal for controlling an activation of the initialization signal during an initial operation in response to the bank active information pulse and a power-up signal;

a period pulse generation unit for generating a period pulse, which is activated periodically, in response to the oscillation enable signal; and

a logic combination unit for generating the initialization signal in response to the bank active information signal, the bank active information pulse, the power-up signal, the period pulse, and the initial control signal.

8. The multi-port memory device as recited in claim 7 , wherein the pulse generation unit includes:

a first delay circuit configured to receive the bank active information signal;

a first inverter configured to receive an output of the first delay circuit; and

a first NAND gate configured to receive an output of the first inverter and the bank active information signal and generate the bank active information pulse.

9. The multi-port memory device as recited in claim 8 , wherein the pulse processing unit includes:

a pull-up PMOS transistor having a gate receiving the bank active information pulse;

a pull-down NMOS transistor having a gate receiving the power-up signal; and

a delay circuit configured to receive the oscillation enable signal, which is outputted through an output terminal of the pull-up PMOS transistor and pull-down NMOS transistor.

10. The multi-port memory device as recited in claim 9 , wherein the period pulse generation unit includes:

a ring oscillator for performing an oscillation in response to the oscillation enable signal;

a third delay circuit configured to receive an output of the ring oscillator;

a second inverter configured to receive an output of the third delay circuit;

a second NAND gate configured to receive an output of the second inverter and the output of the ring oscillator;

a first NOR gate configured to receive the output of the second inverter and the output of the ring oscillator;

a third inverter configured to receive an output of the second NAND gate;

a second NOR gate configured to receive an output of the third inverter and an output of the first NOR gate; and

a fourth inverter configured to receive an output of the second NOR gate and output the period pulse.

11. The multi-port memory device as recited in claim 10 , wherein the logic combination unit includes:

a third NAND gate configured to receive the bank active information signal, the period pulse, and an inverted power-up signal;

a third NOR gate configured to receive the bank active information pulse and the initial control signal;

a fifth inverter configured to receive an output of the third NOR gate; and

a fourth NAND gate configured to receive an output of the third NAND gate and an output of the fifth inverter and output the initialization signal.