CMOS output buffer circuit
View Patent ↗A CMOS output buffer circuit comprises an input unit, a compensation control unit, a first switching unit and a second switching unit. The input unit outputs a data signal in response to a stop signal for determining transmission of the data signal. The compensation control unit determines a power voltage level with reference to the stop signal and the data signal when the data signal is transmitted, and outputs a plurality of compensating signals depending on the power voltage level. The first switching unit including a driving unit driven by the data signal outputted from the input unit and a compensation driving unit driven by combination of the data signal and the plurality of compensating signals compensates change of the power voltage level to output current. The second switching unit operated complementarily with the first switching unit outputs current. Accordingly, the CMOS output buffer circuit supplies a predetermined output current regardless change of a power voltage, thereby reducing power consumption and minimizing overshoot/undershoot noise to stabilize a power supplied to a device.
1. A CMOS output buffer circuit comprising:
an input unit for transmitting a data signal in response to a stop signal for;
a compensation control unit for determining a power voltage level in response to the stop signal and the data signal when the data signal is transmitted and for outputting a plurality of compensating signals depending on the power voltage level;
a first switching unit to output first current, wherein the first switching unit a driving unit comprises driven by an output data signal outputted from the input unit and a compensation driving unit driven by combination of the output data signal and the plurality of compensating signals to compensate change of the power voltage level; and
a second switching unit operated to output a second current complementarily with the first switching unit.
2. The circuit according to claim 1 , wherein the compensation control unit comprises:
a logic operation unit for performing a logic operation on the stop signal and the data signal;
a plurality of buffers for buffering an output signal from the logic operation unit;
an inverting unit for inverting the output signal from the logic operation unit; and
a power voltage level detecting unit enabled by an output signal from one of the plurality of buffers when the data signal is at a low level, to detect and latch the power voltage level by using an output signal from the inverting unit as a clock and to output the plurality of compensating signals when the data signal is at a high level.
3. The circuit according to claim 2 , wherein the power voltage level detecting unit comprises:
a plurality of sub-power level detectors enabled when the stop signal and the data signal are at the low level, to detect the power voltage level and to output a plurality of detecting signals depending on the power voltage level; and
a plurality of latch units for latching the plurality of detecting signals and outputting the plurality of compensating signals when the data signal is at the high level.
4. The circuit according to claim 3 , wherein each of the plurality of the sub-power level detectors comprises:
a PMOS transistor having a source connected to a power voltage and controlled by the output signal from the one of the plurality of buffers;
a first resistor having one side connected to a drain of the PMOS transistor;
a second resistor having one side connected to the other side of the first resistor;
an NMOS transistor having a gate and a drain connected to the other side of the second resistor, and a source to receive a ground voltage; and
an inverting unit for inverting an output signal from the common node of the first resistor and the second resistor.
5. The circuit according to claim 4 , wherein said each of the plurality of the sub-power level detectors generates a reference voltage based on the first resistor, the second resistor and the NMOS transistor, and detects the power voltage level by comparing the power voltage with the generated reference voltage.
6. The circuit according to claim 1 , wherein the compensation driving unit comprises:
a first compensation driving unit switched by a first compensating signal of the plurality of compensating signals corresponding to the power voltage level of 5.0V˜5.5V when the data signal is transmitted;
a second compensation driving unit switched by a second compensating signal of the plurality of compensating signals corresponding to the power voltage level of 4.5V˜5.0V when the data signal is transmitted;
a third compensation driving unit switched by a third compensating signal of the plurality of compensating signals corresponding to the power voltage level of 4.0V˜4.5V when the data signal is transmitted;
a fourth compensation driving unit switched by a fourth compensating signal of the plurality of compensating signals corresponding to the power voltage level of 3.5V˜4.0V when the data signal is transmitted; and
a fifth compensation driving unit switched by a fifth compensating signal of the plurality of compensating signals corresponding to the power voltage level of 3.0V˜3.5V when the data signal is transmitted.
7. The circuit according to claim 6 , wherein each of the first to the fifth compensation driving units comprises:
a logic operation unit for performing a logic operation on the respective corresponding compensating signal;
a buffer for buffering an output signal from the logic operation unit; and
a PMOS transistor switched by an output signal from the buffer.
8. The circuit according to claim 1 , wherein the driving unit comprises:
a logic operation unit for performing a logic operation on the output data signal from the input unit;
a buffer for buffering an output signal from the logic operation unit; and
a PMOS transistor switched by an output signal from the buffer.
9. The circuit according to claim 1 , wherein the second switching unit is an NMOS transistor.