Method for manufacturing flash memory device and flash memory device
View Patent ↗The present invention relates to a method for manufacturing a flash memory device and a flash memory device manufactured by the same. In the present invention, an annealing process of a tunnel insulating film is performed at a relatively low temperature to optimize the threshold voltage of a NHVN transistor. Furthermore, in case of portions not compensated through the annealing process of the tunnel insulating film, the quality of the tunnel insulating film is compensated through a subsequent liner oxide film deposition process and a HDP oxide film annealing process. Therefore, the present invention can improve reliability of the tunnel insulating film and thus provide a flash memory device having good properties.
1. A method for manufacturing a flash memory device, comprising the steps of:
forming a pure oxide layer on a semiconductor by performing a wet oxidization process;
forming an oxynitride film as a tunnel insulating film by performing a first annealing process to the pure oxide layer;
forming a first polysilicon film on the tunnel insulating film;
forming a pad nitride film on the first polysilicon film;
forming a trench by selectively etching the pad nitride film, the first polysilicon film, the tunnel insulating film and the semiconductor substrate;
forming a wall oxide film at the sidewall of the trench;
forming a liner oxide film on the wall oxide film and the sidewall of the pad nitride film;
performing a second annealing process;
forming a first oxide film and filling the trench with the first oxide;
performing a third annealing process to the first oxide film;
removing the pad nitride film;
forming a second polysilicon film on the first polysilicon layer exposed by removing the pad nitride film, wherein the first polysilicon film and the second polysilicon film form a floating gate;
forming a dielectric film on the entire structure having the second polysilicon layer;
forming a control gate on the dielectric film; and
forming source/drain regions in the semiconductor substrate exposed between the control gate and a second gate.
2. The method as claimed in claim 1 , wherein edges of the second polysilicon layer is overlapped with the first oxide layer.
3. The method as claimed in claim 1 , wherein the step of forming the control gate includes:
forming a third polysilicon film on the dielectric film;
forming a tungsten silicide layer on the third polysilicon film; and
patterning the tungsten layer and the third polysilicon film.
4. The method as claimed in claim 1 , wherein the first oxide film is formed with high-density plasma (HDP).
5. The method as claimed in claim 1 , wherein the first annealing process to the pure oxide is performed by using a N 2 gas.
6. The method as claimed in claim 1 , wherein the wet oxidization process is performed under a temperature condition of 750° C. to 850° C.
7. The method as claimed in claim 5 , wherein the first annealing process is under a temperature condition of 900° C. to 910° C.
8. The method as claimed in claim 7 , wherein the first annealing process is performed for 20 to 30 minutes.
9. The method as claimed in claim 1 , wherein the first annealing process to the pure oxide is performed by using a N 2 O gas.
10. The method as claimed in claim 9 , wherein the first annealing process is performed by supplying the N 2 O gas of 10 slm for 10 to 30 minutes.
11. The method as claimed in claim 9 , wherein the first annealing process is performed under a temperature condition of 900° C. to 950° C.
12. The method as claimed in claim 9 , wherein the first annealing process further includes the step of performing a post annealing process using a N 2 gas under a temperature condition of 900° C. to 950° C. for 5 to 30 minutes after the first annealing process.
13. The method as claimed in claim 1 , wherein the step of forming the wall oxide film is performed by a dry oxidization process under a temperature condition of 700° C. to 1000° C.
14. The method as claimed in claim 1 , wherein the second annealing process to the liner oxide film is performed under a temperature condition of 800° C. to 850° C.
15. The method as claimed in claim 1 , wherein the liner oxide film is formed in thickness of 30 Å to 200 Å.
16. The method as claimed in claim 1 , wherein the third annealing process is performed using a N 2 gas under a temperature condition of 800° C. to 950° C.
17. The method as claimed in claim 16 wherein N 2 gas is supplied 5 slm to 20 slm.
18. The method as claimed in claim 1 , wherein the third annealing process is performed for 30 to 120 minutes.