IP Library Granted Patent US 7,169,670
Granted Patent B2
US 7,169,670 · App. 10/880,691 · Granted Jan 30, 2007

Method of forming gate oxide layer in semiconductor device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,169,670
App. No.
10/880,691
Granted
Jan 30, 2007
Kind
B2
Abstract

Provided is related to a method of forming a semiconductor device comprises steps of: providing a semiconductor substrate having a low voltage region and a high voltage region; forming a pad oxide layer and a pad nitride layer in sequence on the semiconductor substrate; removing the pad nitride layer and the pad oxide layer on the semiconductor substrate of the high voltage region, wherein a surface of the semiconductor substrate of the high voltage region is exposed and recessed; forming a sacrificial oxide layer on the surface of the semiconductor substrate of the high voltage region; removing the sacrificial layer; forming a first gate oxide layer on the surface of the semiconductor substrate of the high voltage region; removing the pad oxide layer and the pad nitride layer left on the semiconductor substrate of the low voltage region, wherein a surface of the semiconductor substrate of the low voltage region is exposed and recessed; and forming a second gate oxide layer on the first gate oxide layer and the surface of the semiconductor substrate of the low voltage region.

Claims (16)

1. A method of forming a semiconductor device comprises steps of:

providing a semiconductor substrate having a low voltage region and a high voltage region;

forming a pad oxide layer and a pad nitride layer in sequence on the semiconductor substrate;

removing the pad nitride layer, the pad oxide layer, and a portion of the semiconductor substrate of the high voltage region so that a surface of the semiconductor substrate of the high voltage region is exposed and recessed;

forming a sacrificial layer on the recessed portion of the semiconductor substrate of the high voltage region;

removing the sacrificial layer;

forming a first gate oxide layer on the surface of the semiconductor substrate of the high voltage region;

removing the pad oxide layer and the pad nitride layer left on the semiconductor substrate of the low voltage region, wherein a surface of the semiconductor substrate of the low voltage region is exposed and recessed; and

forming a second gate oxide layer on the first gate oxide layer and the surface of the semiconductor substrate of the low voltage region.

2. The method of forming a semiconductor device of claim 1 , further comprising the steps of: forming a photoresist pattern on the pad nitride layer on the semiconductor substrate of the low voltage region; and removing the photoresist pattern after removing the pad nitride layer and the pad oxide layer on the semiconductor substrate of the high voltage region.

3. The method of forming a semiconductor device of claim 2 , wherein the step of removing the pad nitride layer and the pad oxide layer on the semiconductor substrate of the high voltage region includes the step of performing a wet etching process with the photoresist pattern as an etch mask.

4. The method of forming a semiconductor device of claim 1 , the sacrificial layer is formed with an oxide layer.

5. The method of forming a semiconductor device of claim 4 , the sacrificial layer is formed to a thickness of about 150˜1000 Å.

6. The method of forming a semiconductor device of claim 1 , the first gate oxide layer is formed to a thickness of about 150˜500 Å.

7. The method of forming a semiconductor device of claim 1 , the first gate oxide layer as well as the second gate oxide layer become a gate oxide layer for a high voltage transistor which is formed on the high voltage region.

8. The method of forming a semiconductor device of claim 7 , the second gate oxide layer become a gate oxide layer for a low voltage transistor which is formed on the low voltage region.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2006
From: LEE, MIN KYU; CHANG, HEE HYUN; KIM, JUM SOO; AHN, JUNG RYUL
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 018713/0604 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2006
From: HYNIX SEMICONDUCTOR INC.
To: HYNIX SEMICONDUCTOR INC.; STMICROELECTRONICS S.R.L.
Reel/Frame 018207/0057 →