Precise time measurement apparatus and method
View Patent ↗A time measurement system that uses two signals generated by direct digital synthesis. The generated signals have the same frequency but different phase. One signal is used to identify the start of the measurement interval and the other signal is used to identify a measurement window in which a signal indicating the end of the measured interval might be detected. The time measurement system is used as part of a time domain reflectometry (TDR) system. An incident pulse is synchronized to the first signal and launched down on a line. In the measurement window, the signal on the line is compared to a threshold value to determine whether the pulse has been reflected and traveled back to the source. By iteratively repeating the measurement with a different measurement window, the time of arrival of the reflected pulse can be determined. This time domain reflectometry approach is incorporated into automatic test equipment for testing semiconductor devices and is used to calibrate the test equipment.
1. Time measurement apparatus comprising:
a) a first clock generation circuit outputting a first clock signal, the first clock generation circuit comprising a first numeric counter oscillator;
b) a second clock generation circuit outputting a second clock signal, the second clock generation circuit comprising a second numeric counter oscillator;
c) a clock input coupled to the first numeric counter oscillator and the second numeric counter oscillator, the clock input controlling the rate at which the first numeric counter oscillator and the second numeric counter oscillator increment;
d) at least one sequencer controlling the operation of the time measurement apparatus, the at least one sequencer generating a first control signal synchronized to the first clock signal and a second control signal synchronized to the second clock signal.
2. The time measurement apparatus of claim 1 wherein the first clock generation circuit and the second clock generation circuit comprise a first direct digital synthesis circuit and a second direct digital synthesis circuit, respectively.
3. The time measurement apparatus of claim 1 wherein the first clock generation circuit additionally comprises a look-up table having an address input and an output, and the output of the first numeric counter oscillator is applied to the address input of the look-up table.
4. The time measurement apparatus of claim 3 wherein the first clock generation circuit additionally comprises an digital to analog converter having a digital input and an analog output, and the digital input is coupled to the output of the look-up table.
5. The time measurement apparatus of claim 4 wherein the second clock generation circuit additionally comprises a second look-up table having an address input and an output, and the output of the second numeric counter oscillator is applied to the address input of the second look-up table.
6. The time measurement apparatus of claim 5 wherein the second clock generation circuit additionally comprises a second digital to analog converter having a digital input and an analog output, and the digital input is coupled to the output of the second look-up table.
7. The time measurement apparatus of claim 1 additionally comprising a driver circuit having a timing input and a measurement circuit having a timing input, wherein the timing input of the driver circuit is coupled to the first control signal and the timing input of the measurement circuit is coupled to the second control signal.
8. The time measurement apparatus of claim 7 wherein the measurement circuit comprises a comparator.
9. The time measurement apparatus of claim 8 wherein the driver circuit and the comparator circuit comprise pin electronics in a channel of automatic test equipment for semiconductor devices.
10. The time measurement apparatus of claim 7 additionally comprising a first flip-flop having a clock input and an output coupled to the driver and a second flip-flop having a clock input and a data input coupled to the comparator, the clock input of the first flip-flop coupled to the first control signal and the clock input of the second flip-flop coupled to the second control signal.
11. A method of measuring a time difference comprising:
a) generating a first clock having a first frequency, the frequency controlled in response to at least one value;
b) generating a second clock having a second frequency, correlated to the first frequency, with the frequency and phase of the second clock relative to the phase of the first clock being controlled in response to at least one digital value;
c) starting a measurement interval synchronized to the first clock; and
d) ending the measurement interval synchronized to the second clock.
12. The method of measuring a time difference of claim 11 wherein the first clock and the second clock have the same frequency and a different phase.
13. The method of claim 11 additionally comprising:
comparing a signal to a value defining an event at the end of the measurement interval.
14. The method of claim 13 additionally comprising:
repeating for a plurality of iterations the steps of generating a first clock, generating a second clock, starting a measurement interval, ending the measurement interval and comparing the signal; and
wherein, for each of the plurality of iterations, the phase of the second clock relative to the first clock is controlled to provide a different relative phase.
15. The method of claim 13 additionally comprising:
collecting a data set by repetitively starting a measurement interval; ending the measurement interval and comparing the signal value and a value in the data set is generated for each comparison; wherein,
i) for each of the plurality of repetitions, the phase of the second clock relative to the first clock is controlled to provide the same relative phase;
ii) comparing a signal comprises comparing the signal to a binary threshold and an event is defined by the data set having a specified percentage of values of a first digital value.
16. The method of claim 11 additionally comprising:
a) transmitting a signal at the beginning of the measurement interval; and
b) measuring a signal at the end of the measurement interval.
17. The method of claim 16 wherein the time measurement is used in a TDR measurement.
18. A method of measuring a time difference comprising:
a) generating a first clock having a first frequency, the frequency controlled in response to at least one digital value;
b) generating a second clock having a second frequency, correlated to the first frequency, with the frequency and phase of the second clock relative to the phase of the first clock being controlled, in response to at least one digital value;
c) starting a measurement interval synchronized to the first clock;
d) ending the measurement interval synchronized to the second clock;
wherein the first clock and the second clock have the same frequency and a different phase;
wherein the first clock is generated with a first direct digital synthesis circuit including a first numeric counter oscillator having a first phase increment register and the second clock is generated with a second direct digital synthesis circuit including a second numeric counter oscillator having a second phase increment register; and
wherein generating a first clock and a second clock comprises loading the same value into the first and second phase increment registers.
19. The method of measuring a time difference of claim 18 , wherein the first numeric counter oscillator has a first phase accumulator register and the second numeric counter oscillator has a second phase accumulator register, wherein generating a first clock and a second clock comprises initializing the first phase accumulator register and the second phase accumulator register to have different values.
20. A method of measuring a time difference comprising:
a) generating a first clock having a first frequency, the frequency controlled in response to at least one digital value;
b) generating a second clock having a second frequency, correlated to the first frequency, with the frequency and phase of the second clock relative to the phase of the first clock being controlled, in response to at least one digital value;
c) starting a measurement interval synchronized to the first clock;
d) ending the measurement interval synchronized to the second clock;
wherein the first clock and the second clock have the same frequency and a different phase;
wherein the first clock is generated with a first direct digital synthesis circuit including a first numeric counter oscillator having a first phase accumulator register, and the second clock is generated with a second direct digital synthesis circuit including a second numeric counter oscillator having a second phase accumulator register; and
wherein generating a first clock and a second clock comprises initializing the first phase accumulator register and the second phase accumulator register to have different values.