Floating gate semiconductor component and method of manufacture
View Patent ↗A semiconductor component having a substantially planar surface on which a film can be deposited and a method for manufacturing the semiconductor component. A layer of dielectric material is formed over a semiconductor substrate and a layer of polysilicon is formed on the layer of dielectric material. The polysilicon layer is patterned to form floating gate structures and expose portions of the layer of dielectric material. Additional dielectric material is formed over the floating gate structures and the exposed portions of the layer of dielectric material. The additional dielectric material is planarized such that it has a surface that is substantially contiguous with and coplanar with the floating gate structures. An oxide-nitride-oxide (ONO) dielectric structure or stack is formed on the surfaces of the floating gate structures and the dielectric material. A layer of polysilicon is formed on the ONO dielectric structure.
1. A method for manufacturing a floating gate semiconductor component, comprising:
providing a semiconductor substrate having an active region and an isolation structure;
forming a first layer of dielectric material on the active region and the isolation structure of the semiconductor substrate;
forming a first layer of semiconductor material over the active region and the isolation structure, wherein a first portion of the first layer of dielectric material is between the active region and the first layer of semiconductor material and a second portion of the first layer of dielectric material is between the isolation structure and the first layer of semiconductor material;
forming a second layer of dielectric material on the first layer of dielectric material and over the isolation structure; and
planarizing the second layer of dielectric material wherein, after planarizing the second layer of dielectric material, the first portion of the first layer of dielectric material that is between the semiconductor substrate and the first layer of semiconductor material and the second portion of the first layer of dielectric material that is between the isolation structure and the first layer of semiconductor material remain.
2. The method of claim 1 , wherein providing the semiconductor substrate includes providing the active region adjacent the isolation structure.
3. The method of claim 1 , wherein forming the first layer of semiconductor material includes forming a polycrystalline semiconductor material.
4. The method of claim 1 , wherein the polycrystalline semiconductor material is polysilicon.
5. The method of claim 1 , wherein providing the semiconductor substrate includes providing first and second active regions and providing the isolation structure between the first and second active regions.
6. The method of claim 5 , further including forming a dielectric material on the second layer of dielectric material.
7. The method of claim 6 , wherein forming the dielectric material includes forming an oxide-nitride-oxide (ONO) dielectric material on the second layer of dielectric material.
8. The method of claim 6 , further including forming a second layer of semiconductor material over the dielectric material.
9. The method of claim 8 , wherein the second layer of semiconductor material is polysilicon.
10. The method of claim 1 , wherein planarizing the second layer of dielectric material includes using a technique selected from the group of techniques consisting of chemical mechanical planarization, electropolishing, electrochemical polishing, chemical polishing, and chemical enhanced planarization.
11. A method for manufacturing a memory element, comprising:
providing a semiconductor substrate;
forming a plurality of isolation structures in the semiconductor substrate, wherein a first active region of the semiconductor substrate is between first and second isolation structures of the plurality of isolation structures;
forming a first finger of semiconductor material over the first active region and at least the first isolation structure of the plurality of isolation structures;
disposing dielectric material over the first finger of semiconductor material and the first and second isolation structures;
planarizing the dielectric material to have a substantially planar surface, wherein the first finger of semiconductor material over the first active region and at least the first isolation structure of the plurality of isolation structures remains after planarizing the dielectric material;
forming an electrical isolation material on the substantially planar surface; and
forming a layer of semiconductor material over the electrical isolation material.
12. The method of claim 11 , wherein forming the first finger of semiconductor material comprises:
forming a layer of polysilicon on the first active region and the first and second isolation structures; and
patterning the layer of polysilicon using a photolithographic technique to form the first finger of semiconductor material.
13. The method of claim 12 , wherein forming the electrical isolation material comprises:
forming a first layer of oxide on the substantially planar surface;
forming a layer of nitride on the layer of oxide; and
forming a second layer of oxide on the layer of nitride, wherein the first layer of oxide, the layer of nitride, and the second layer of oxide cooperate to form an oxide-nitride-oxide (ONO) stack.
14. The method of claim 13 , wherein forming the layer of semiconductor material on the electrical isolation material includes forming polysilicon on the electrical isolation material.
15. The method of claim 14 , wherein forming the finger of semiconductor material further includes forming a layer of dielectric material on the first active region, a portion of the layer of dielectric material between the first active region and the first finger of semiconductor material.
16. The method of claim 11 , wherein forming the plurality of isolation structures includes forming a third isolation structure in the semiconductor substrate and a second active region between the second isolation structure and the third isolation structure.
17. The method of claim 16 , further including forming a second finger of semiconductor material, the second finger over the second active region.
18. The method of claim 17 , wherein forming the first and second fingers of semiconductor material comprises:
forming a layer of polysilicon on the first and second active regions and the first, second, and third isolation structures; and
patterning the layer of polysilicon using a photolithographic technique to form the first and second fingers of semiconductor material.
19. The method of claim 18 , wherein forming the electrical isolation material comprises:
forming a first layer of oxide on the substantially planar surface;
forming a layer of nitride on the layer of oxide; and
forming a second layer of oxide on the layer of nitride, wherein the first layer of oxide, the layer of nitride, and the second layer of oxide cooperate to form an oxide-nitride-oxide (ONO) stack.
20. A semiconductor component, comprising:
a semiconductor substrate having a plurality of isolation structures, wherein a first active region of the semiconductor substrate is between first and second isolation structures of the plurality of isolation structures;
a first finger of semiconductor material disposed over the first active region and the first isolation structure, the first finger of semiconductor material having a surface;
a second finger of semiconductor material disposed over the first active region and the second isolation structure the second finger of semiconductor material having a surface;
a first dielectric material disposed over the active region between the first and second fingers of semiconductor material, the first dielectric material having a surface the surfaces of the first and second fingers of semiconductor material and the surface of the first dielectric material being substantially coplanar;
a second dielectric material disposed on the surfaces of the first and second fingers of semiconductor material and the first dielectric material; and
a layer of semiconductor material disposed over the second dielectric material.
21. The semiconductor component of claim 20 , wherein the first finger of semiconductor material comprises polysilicon.