IP Library Granted Patent US 7,315,080
Granted Patent B1
US 7,315,080 · App. 10/885,965 · Granted Jan 1, 2008

Ball grid array package that includes a collapsible spacer for separating die adapter from a heat spreader

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Quick Facts
Patent No.
US 7,315,080
App. No.
10/885,965
Granted
Jan 1, 2008
Kind
B1
Abstract

A ball grid array package is manufactured by mounting a semiconductor die to a first surface of a substrate and mounting a die adapter to the semiconductor die. The semiconductor die is wire bonded to ones of conductive traces of the substrate. A collapsible spacer is mounted to the substrate and the substrate is releasably clamped to an upper side of a mold cavity. A heat spreader and at least one collapsible spacer are placed in the mold cavity such that the collapsible spacer is disposed between the heat spreader and the substrate. A molding compound is molded in the mold, thereby molding the semiconductor die, the substrate, the wire bonds, the die adapter, the at least one collapsible spacer and the heat spreader into the molding compound to provide a molded package. A ball grid array is formed on a second surface of the substrate, bumps of the ball grid array being electrically connected to the conductive traces and the integrated circuit package is singulated.

Claims (28)

1. An integrated circuit package comprising:

a substrate having a plurality of conductive traces;

a semiconductor die mounted on a first surface of said substrate;

a die adapter mounted on said semiconductor die;

a plurality of wire bonds between said semiconductor die and ones of said conductive traces;

a heat spreader disposed proximal to and spaced from said die adapter by at least one collapsible spacer, wherein the collapsible spacer is a substantially spherical ball;

a molding compound encapsulating the semiconductor die, the wire bonds, the die adapter and said collapsible spacer between the substrate and the heat spreader; and

a ball grid array on a second surface of said substrate, bumps of said ball grid array being electrically connected to said conductive traces.

2. The integrated circuit package according to claim 1 , wherein said at least one collapsible spacer comprises a collapsible spacer disposed between and in contact with said heat spreader and said die adapter.

3. The integrated circuit package according to claim 1 , wherein wire bonding further comprises ground wire bonding said semiconductor die to at least one ground pad on said substrate.

4. An integrated circuit package comprising:

a substrate having a plurality of conductive traces;

a semiconductor die mounted on a first surface of said substrate;

a die adapter mounted on said semiconductor die;

a plurality of wire bonds between said semiconductor die and ones of said conductive traces;

a heat spreader disposed proximal to and spaced from said die adapter by at least one collapsible spacer;

a molding compound encapsulating the semiconductor die, the wire bonds, the die adapter and said collapsible spacer between the substrate and the heat spreader; and

a ball grid array on a second surface of said substrate, bumps of said ball grid array being electrically connected to said conductive traces,

wherein said at least one collapsible spacer further comprises a plurality of collapsible spacers disposed between and in contact with said heat spreader and said substrate array.

5. An integrated circuit package comprising:

a substrate having a plurality of conductive traces;

a semiconductor die mounted on a first surface of said substrate;

a die adapter mounted on said semiconductor die;

a plurality of wire bonds between said semiconductor die and ones of said conductive traces;

a heat spreader disposed proximal to and spaced from said die adapter by at least one collapsible spacer;

a molding compound encapsulating the semiconductor die, the wire bonds, the die adapter and said collapsible spacer between the substrate and the heat spreader; and

a ball grid array on a second surface of said substrate, bumps of said ball grid array being electrically connected to said conductive traces,

wherein wire bonding further comprises ground wire bonding said semiconductor die to said die adapter.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE ADD ANNEX INADVERTENTLY LEFT OUT ORIGINAL ASSIGNMENT DOCUMENT PREVIOUSLY RECORDED AT REEL: 037880 FRAME: 0534. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 8, 2016
From: UTAC HONG KONG LIMITED
To: UTAC HEADQUARTERS PTE. LTD.
Reel/Frame 039822/0591 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2016
From: UTAC HONG KONG LIMITED
To: UTAC HEADQUARTERS PTE. LTD.
Reel/Frame 037880/0534 →
CHANGE OF NAME Recorded Oct 29, 2010
From: ASAT LIMITED
To: UTAC HONG KONG LIMITED
Reel/Frame 025217/0410 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS - SECOND PRIORITY Recorded Jun 29, 2010
From: UTAC HONG KONG LIMITED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024599/0827 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS - FIRST PRIORITY Recorded Jun 29, 2010
From: UTAC HONG KONG LIMITED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024599/0743 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS - SECOND PRIORITY Recorded Jun 29, 2010
From: UTAC HONG KONG LIMITED
To: THE HONGKONG AND SHANGHAI BANKING CORPORATION LIMITED, AS SECURITY AGENT
Reel/Frame 024611/0097 →
NUNC PRO TUNC ASSIGNMENT Recorded Apr 20, 2010
From: FAN, CHUN HO; LAM, WING KEUNG; SZE, MING WANG; LABEEB, SADAK THAMBY; MCLELLAN, NEIL; KIRLOSKAR, MOHAN
To: ASAT LIMITED
Reel/Frame 024252/0882 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 12, 2005
From: FAN, CHUN HO; MARTIN, JOSEPH ANDREW; SZE, MING WANG; YEUNG, TAK SANG
To: ASAT LTD.
Reel/Frame 016876/0145 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 7, 2005
From: FAN, CHUN HO; MARTIN, JOSEPH ANDREW; SZE, MING WANG; YEUNG, TAK SANG
To: ASAT LTD.
Reel/Frame 016859/0186 →