IP Library Granted Patent US 7,254,659
Granted Patent B2
US 7,254,659 · App. 10/899,611 · Granted Aug 7, 2007

Method of VMEbus split-read transaction

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Quick Facts
Patent No.
US 7,254,659
App. No.
10/899,611
Granted
Aug 7, 2007
Kind
B2
Abstract

A method of performing a VMEbus split-read transaction ( 701 ) includes providing a master VMEbus module ( 502 ) coupled to a slave VMEbus module ( 504 ) through a VMEbus network ( 506 ). The master VMEbus module initiates a VMEbus split-read transaction request ( 524 ) in a VME address encoding phase ( 601 ) to the slave VMEbus module, where the VMEbus split-read transaction request comprises a return address ( 660 ) for the VMEbus master module in the VMEbus address encoding phase, and where the VMEbus split-read transaction request requests a set of data ( 544 ). The master VMEbus module releases the VMEbus network and the slave VMEbus module acquires the VMEbus network. The slave VMEbus module places the set of data on the VMEbus network, where the set of data comprises the return address for the VMEbus master module, and the master VMEbus module retrieves the set of data.

Claims (36)

1. A method of performing a VMEbus split-read transaction, comprising:

providing a master VMEbus module coupled to a slave VMEbus module through a VMEbus network;

the master VMEbus module initiating a VMEbus split-read transaction request in a VME address encoding phase to the slave VMEbus module, wherein the VMEbus split-read transaction request comprises a return address for the master VMEbus module in the VME address encoding phase, and wherein the VMEbus split-read transaction request requests a set of data;

the master VMEbus module releasing the VMEbus network;

the slave VMEbus module acquiring the VMEbus network;

the slave VMEbus module placing the set of data on the VMEbus network, wherein the set of data comprises the return address for the master VMEbus module; and

the master VMEbus module retrieving the set of data.

2. The method of claim 1 , further comprising the slave VMEbus module acknowledging the VMEbus split-read transaction request.

3. The method of claim 1 , wherein initiating the VMEbus split-read transaction request comprises providing a split-read transaction code to the slave VMEbus module.

4. The method of claim 3 , wherein the split-read transaction code is an XAM code.

5. The method of claim 1 , further comprising after releasing the VMEbus network, the VMEbus network performing other VMEbus network activity prior to the slave VMEbus module acquiring the VMEbus network.

6. The method of claim 1 , wherein initiating the VMEbus split-read transaction request initiates a split-read timer period at the master VMEbus module.

7. The method of claim 6 , wherein if the slave VMEbus module fails to acknowledge the VMEbus split-read transaction request prior to expiration of the split-read timer period, the VMEbus split-read transaction request expires.

8. The method of claim 1 , wherein the return address is included in an address phase three of the VME address encoding phase.

9. The method of claim 1 , wherein a length code is included in an address phase two of the VME address encoding phase.

10. The method of claim 1 , further comprising the master VMEbus module recognizing the return address for the set of data placed on the VMEbus network by the slave VMEbus module.

11. The method of claim 1 , wherein the return address comprises a master VMEbus module memory address destination for the set of data requested.

12. The method of claim 11 , wherein the master VMEbus module retrieving the set of data comprises the master VMEbus module writing the set of data to the master VMEbus module memory address destination.

13. A computer-readable medium containing computer instructions for instructing a processor to perform a VMEbus split-read transaction, the instructions comprising:

providing a master VMEbus module coupled to a slave VMEbus module through a VMEbus network;

the master VMEbus module initiating a VMEbus split-read transaction request in a VME address encoding phase to the slave VMEbus module, wherein the VMEbus split-read transaction request comprises a return address for the master VMEbus module in the VME address encoding phase, and wherein the VMEbus split-read transaction request requests a set of data;

the master VMEbus module releasing the VMEbus network;

the slave VMEbus module acquiring the VMEbus network;

the slave VMEbus module placing the set of data on the VMEbus network, wherein the set of data comprises the return address for the master VMEbus module; and

the master VMEbus module retrieving the set of data.

14. The computer-readable medium of claim 13 , further comprising the slave VMEbus module acknowledging the VMEbus split-read transaction request.

15. The computer-readable medium of claim 13 , wherein initiating the VMEbus split-read transaction request comprises providing a split-read transaction code to the slave VMEbus module.

16. The computer-readable medium of claim 15 , wherein the split-read transaction code is an XAM code.

17. The computer-readable medium of claim 13 , further comprising after releasing the VMEbus network, the VMEbus network performing other VMEbus network activity prior to the slave VMEbus module acquiring the VMEbus network.

18. The computer-readable medium of claim 13 , wherein initiating the VMEbus split-read transaction request initiates a split-read timer period at the master VMEbus module.

19. The computer-readable medium of claim 18 , wherein if the slave VMEbus module fails to acknowledge the VMEbus split-read transaction request prior to expiration of the split-read timer period, the VMEbus split-read transaction request expires.

20. The computer-readable medium of claim 13 , wherein the return address is included in an address phase three of the VME address encoding phase.

21. The computer-readable medium of claim 13 , wherein a length code is included in an address phase two of the VME address encoding phase.

22. The computer-readable medium of claim 13 , further comprising the master VMEbus module recognizing the return address for the set of data placed on the VMEbus network by the slave VMEbus module.

23. The computer-readable medium of claim 13 , wherein the return address comprises a master VMEbus module memory address destination for the set of data requested.

24. The computer-readable medium of claim 23 , wherein the master VMEbus module retrieving the set of data comprises the master VMEbus module writing the set of data to the master VMEbus module memory address destination.

Assignments (11)
PATENT SECURITY AGREEMENT Recorded Jun 30, 2025
From: CREELED, INC.; PENGUIN SOLUTIONS CORPORATION (DE); SMART EMBEDDED COMPUTING, INC.; SMART HIGH RELIABILITY SOLUTIONS LLC; SMART MODULAR TECHNOLOGIES, INC.; PENGUIN COMPUTING, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 071755/0001 →
RELEASE OF PATENT SECURITY INTEREST RECORDED AT R/F 058983/0001 Recorded Jun 25, 2025
From: CITIZENS BANK, N.A.
To: SMART MODULAR TECHNOLOGIES, INC.; SMART EMBEDDED COMPUTING, INC.; SMART HIGH RELIABILITY SOLUTIONS LLC; CREELED, INC.
Reel/Frame 071725/0207 →
SECURITY INTEREST Recorded Feb 7, 2022
From: SMART MODULAR TECHNOLOGIES, INC.; SMART HIGH RELIABILITY SOLUTIONS, LLC; SMART EMBEDDED COMPUTING, INC.; CREELED, INC.
To: CITIZENS BANK, N.A.
Reel/Frame 058983/0001 →
CHANGE OF NAME Recorded Jun 24, 2020
From: ARTESYN EMBEDDED COMPUTING, INC.
To: SMART EMBEDDED COMPUTING, INC.
Reel/Frame 053023/0953 →
CHANGE OF NAME Recorded Jun 18, 2020
From: EMERSON NETWORK POWER - EMBEDDED COMPUTING, INC.
To: ARTESYN EMBEDDED COMPUTING, INC.
Reel/Frame 052978/0634 →
RELEASE OF SECURITY INTEREST Recorded Jul 9, 2019
From: ARTESYN EMBEDDED COMPUTING, INC. (F/K/A EMERSON NETWORK POWER - EMBEDDED COMPUTING, INC.)
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049698/0222 →
PARTIAL RELEASE OF SECURITY INTEREST Recorded Jul 8, 2019
From: BANK OF AMERICA, N.A.
To: ARTESYN EMBEDDED COMPUTING, INC. (F/K/A EMERSON NETWORK POWER - EMBEDDED COMPUTING, INC.)
Reel/Frame 049694/0096 →
SECURITY AGREEMENT Recorded Nov 26, 2013
From: ARTESYN TECHNOLOGIES, INC.; ARTESYN NORTH AMERICA LLC; EMERSON NETWORK POWER - EMBEDDED COMPUTING, INC.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 031731/0048 →
SECURITY AGREEMENT Recorded Nov 25, 2013
From: ARTESYN TECHNOLOGIES, INC.; ARTESYN NORTH AMERICA LLC; EMERSON NETWORK POWER - EMBEDDED COMPUTING, INC.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT AND GRANTEE
Reel/Frame 031719/0417 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2008
From: MOTOROLA, INC.
To: EMERSON NETWORK POWER - EMBEDDED COMPUTING, INC.
Reel/Frame 020540/0714 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2004
From: HARRIS, JEFFREY M.; RUSH, MALCOLM J.
To: MOTOROLA, INC.
Reel/Frame 015630/0898 →