IP Library Granted Patent US 7,180,160
Granted Patent B2
US 7,180,160 · App. 10/903,722 · Granted Feb 20, 2007

MRAM storage device

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Quick Facts
Patent No.
US 7,180,160
App. No.
10/903,722
Granted
Feb 20, 2007
Kind
B2
Abstract

A MRAM storage device comprises a substrate, on/above of which a plurality of word lines, a plurality of bit lines, a plurality of memory cells, and a plurality of isolation diodes are provided. Each memory cell forms a resistive cross point of one word line and one bit line, respectively. Each memory cell is connected to one isolation diode such that a unidirectional conductive path is formed from a word line to a bit line via the corresponding memory cell, respectively. The substrate, at least a part of the word lines or at least a part of the bit lines, and the isolation diodes are realized as one common monocrystal semiconductor block.

Claims (42)

1. MRAM storage device comprising:

a substrate;

a plurality of word lines;

a plurality of bit lines;

a plurality of memory cells; and

a plurality of vertical access devices;

wherein each memory cell forms a resistive cross point of one word line and one bit line, respectively;

wherein each memory cell is connected to one vertical access device such that a unidirectional conductive path is formed from a word line to a bit line via the corresponding memory cell, respectively; and

wherein the substrate, at least a part of the word lines and at least a part of the vertical access device are realized as one common monocrystal semiconductor block.

2. The MRAM storage device of claim 1 , wherein each memory cell together with its corresponding vertical access device constitutes a pillar extending perpendicular to the directions of the word lines and the bit lines.

3. The MRAM storage device of claim 2 , wherein an upper part of each pillar is constituted by the memory cell, and a lower part of each pillar is constituted by the vertical access device.

4. The MRAM storage device of claim 1 , wherein the word lines comprise read word lines and write word lines.

5. The MRAM storage device of claim 4 , wherein each memory cell together with its corresponding vertical access device constitutes a pillar extending perpendicular to the directions of the word lines and the bit lines, wherein the pillars are provided on the read word lines.

6. The MRAM storage device of claim 5 , wherein an upper part of each pillar is constituted by the memory cell, and a lower part of each pillar is constituted by the vertical access device, wherein the vertical access devices contact the read word lines.

7. The MRAM storage device of claim 4 , wherein the write word lines show different horizontal positions than the read word lines, and that the write word lines show overlapping vertical positions with respect to the vertical positions of the memory cells, so that each memory cell is sandwiched by two write word lines being electrically isolated from the memory cells.

8. The MRAM storage device of claim 4 , wherein the write word lines are located above the memory cells and show different horizontal positions than the read word lines.

9. The MRAM storage device of claim 4 , wherein the write word lines are located above the memory cells and show the same horizontal positions than the read word lines.

10. The MRAM storage device of claim 4 , wherein additional read word lines which show different horizontal positions than the read word lines, and which show overlapping vertical positions with respect to the vertical positions of the memory cells, so that each memory cell is sandwiched by two write word lines being electrically connected to the memory cells.

11. The MRAM storage device of claim 4 , wherein junctions between the substrate and read word lines are directly provided onto the substrate in the form of diodes, respectively.

12. The MRAM storage device of claim 1 , wherein said vertical access device is an isolation diode.

13. MRAM storage device comprising:

a substrate;

a plurality of word lines;

a plurality of bit lines;

a plurality of memory cells; and

a plurality of vertical access devices;

wherein each memory cell forms a resistive cross point of one word line and one bit line, respectively;

wherein each memory cell is connected to one vertical access device such that a unidirectional conductive path is formed from a word line to a bit line via the corresponding memory cell, respectively; and

wherein the substrate, at least a part of the bit lines and at least a part of the vertical access device are realized as one common monocrystal semiconductor block.

14. An MRAM storage device comprising:

a substrate;

a plurality of word lines above the substrate;

a plurality of bit lines over the substrate;

a plurality of memory cells over the substrate; and

a plurality of vertical access devices over the substrate;

wherein each memory cell forms a resistive cross point of one word line and one bit line;

wherein each memory cell is connected to one vertical access device such that a unidirectional conductive path is formed from a word line to a bit line via the corresponding memory cell; and

wherein the substrate, at least part of the word lines, at least part of the bit lines and at least part of the vertical access devices are all one common monocrystal semiconductor block.

15. The MRAM storage device of claim 14 , wherein each memory cell together with its corresponding vertical access device constitutes a pillar extending perpendicular to the directions of the word lines and the bit lines.

16. The MRAM storage device of claim 15 , wherein an upper part of each pillar is constituted by the memory cell, and a lower part of each pillar is constituted by the vertical access device.

17. The MRAM storage device of claim 14 , wherein the word lines comprise read word lines and write word lines.

18. The MRAM storage device of claim 17 , wherein each memory cell together with its corresponding vertical access device constitutes a pillar extending perpendicular to the directions of the word lines and the bit lines, wherein the pillars are provided on the read word lines.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023821/0535 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2004
From: FERRANT, RICHARD; BRAUN, DANIEL; LOUIS, PASCAL
To: INFINEON TECHNOLOGIES AG; ALTIS SEMICONDUCTOR
Reel/Frame 016088/0326 →