Via barrier layers continuous with metal line barrier layers at notched or dielectric mesa portions in metal lines
View Patent ↗The present invention provides an interconnect structure that includes a diffusion barrier which is positioned within the structure in a fashion that increases the reliability and lifetime of the interconnect structure.
1. An integrated circuit comprising:
a metal wiring level comprising metal lines within an intralevel dielectric, said metal lines having a first portion with a first width and a notch portion having a second width, wherein said first width is greater than said second width, and wherein said metal lines are separated from said intralevel dielectric by a metal diffusion barrier that is located underneath the metal lines and along sidewalls of the metal lines; and
an interconnect wiring level atop said metal wiring level comprising a via interconnect within an interlevel dielectric, wherein said via interconnect is separated from said interlevel dielectric and in electrical contact to said metal lines of said metal wiring level through a via diffusion barrier that is located underneath the via interconnect and along sidewalls of thy via interconnect, wherein said via diffusion barrier contacts said metal diffusion barrier within said notch portion of said metal lines to form a continuous diffusion barrier between the via interconnect and the notch portion of the metal lines.
2. The interconnect structure of claim 1 wherein said intralevel dielectric and said interlevel dielectric comprise materials having a dielectric constant of about 3.5 or less.
3. The interconnect structure of claim 1 wherein said metal lines and said via interconnects comprise copper, aluminum, gold, silver, or alloys thereof.
4. The interconnect structure of claim 1 wherein said via diffusion barrier and said metal diffusion barrier comprise: tantaulum, tungsten, ruthenium, cobalt, titanium, or nitrides thereof.
5. The interconnect structure of claim 1 wherein said via diffusion barrier and said metal diffusion barrier have a thickness ranging from about 5 nm to about 100 nm.
6. An integrated circuit comprising:
a metal wiring level comprising metal lines within an intralevel dielectric, wherein a mesa portion of said intralevel dielectric is positioned within a portion of said metal lines, wherein said metal lines are separated from said intralevel dielectric, including said mesa portion of said intralevel dielectric, by a moral diffusion barrier that is located underneath the metal lines arid along sidewalls of the metal lines; and
an interconnect wiring level atop said metal wiring level comprising a via interconnect within an interlevel dielectric, wherein said via interconnect is separated from said interlevel dielectric and in electrical contact to said metal lines of said metal wiring level through a via diffusion barrier that is located underneath the via interconnect and along sidewalls of the via interconnect, wherein said via diffusion barrier contacts said metal diffusion barrier within said mesa portion of said intralevel dielectric to form a continuous diffusion barrier between the via interconnect and the mesa portion of the intralevel dielectric.
7. The interconnect structure of claim 6 wherein said intralevel dielectric, including said mesa portion of said interlevel dielectric, comprises materials having a dielectric constant of about 3.5 or less.
8. The interconnect structure of claim 6 wherein said metal lines and said via interconnects comprise copper, aluminum, gold, silver, or alloys thereof.
9. The interconnect structure of claim 6 wherein said via diffusion barrier and said metal diffusion barrier comprise: tantalum, tungsten, ruthenium, cobalt, titanium, or nitrides thereof.
10. The interconnect structure of claim 6 wherein said via diffusion barrier and said metal diffusion barrier have a thickness ranging from about 5 nm to about 100 nm.