Patent Assignment
Reel/Frame 041777/0233
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2017-02-22
Received: 2017-02-22
Pages: 8
Assignor
GLOBALFOUNDRIES INC.
Executed: 2016-12-07
Assignee
AURIGA INNOVATIONS, INC.
303 TERRY FOX DRIVE, SUITE 300, OTTAWA, CAX, K2K 3J1, CANADA
Covered Applications
(89)
BURIED METAL-SEMICONDUCTOR ALLOY LAYERS AND STRUCTURES AND METHODS FOR FABRICATION THEREOF
App. No. 13/607,869
→
TECHNIQUES FOR ENABLING MULTIPLE VT DEVICES USING HIGH-K METAL GATE STACKS
App. No. 13/433,815
→
STRUCTURE AND METHOD FOR MOBILITY ENHANCED MOSFETS WITH UNALLOYED SILICIDE
App. No. 13/397,865
→
STRUCTURE AND METHOD FOR MOBILITY ENHANCED MOSFETS WITH UNALLOYED SILICIDE
App. No. 13/397,860
→
INTEGRATED CIRCUIT STRUCTURES WITH SILICON GERMANIUM FILM INCORPORATED AS LOCAL INTERCONNECT AND/OR CONTACT
App. No. 13/368,416
→
FIN-TYPE FIELD EFFECT TRANSISTOR
App. No. 13/361,050
→
BALL GRID ARRAY AND CARD SKEW MATCHING OPTIMIZATION
App. No. 12/971,239
→
CONTACT METALLURGY STRUCTURE
App. No. 12/967,633
→
INTEGRATED CIRCUIT STRUCTURES WITH SILICON GERMANIUM FILM INCORPORATED AS LOCAL INTERCONNECT AND/OR CONTACT
App. No. 12/815,622
→
METHOD OF FORMING MULTI-HIGH-DENSITY MEMORY DEVICES AND ARCHITECTURES
App. No. 12/794,826
→
SEMICONDUCTOR CHIPS WITH REDUCED STRESS FROM UNDERFILL AT EDGE OF CHIP
App. No. 12/762,404
→
TECHNIQUES FOR ENABLING MULTIPLE VT DEVICES USING HIGH-K METAL GATE STACKS
App. No. 12/720,354
→
METAL INTERCONNECT AND IC CHIP INCLUDING METAL INTERCONNECT
App. No. 12/701,045
→
STRUCTURE AND METHOD FOR FABRICATING SELF-ALIGNED METAL CONTACTS
App. No. 12/566,190
→
USING METAL/METAL NITRIDE BILAYERS AS GATE ELECTRODES IN SELF-ALIGNED AGGRESSIVELY SCALED CMOS DEVICES
App. No. 12/542,087
→
METHOD OF FABRICATING ULTRA-DEEP VIAS AND THREE-DIMENSIONAL INTEGRATED CIRCUITS USING ULTRA-DEEP VIAS
App. No. 12/540,457
→
METHOD OF FABRICATING ULTRA-DEEP VIAS AND THREE-DIMENSIONAL INTEGRATED CIRCUITS USING ULTRA-DEEP VIAS
App. No. 12/540,490
→
STRUCTURE AND METHOD FOR CREATING RELIABLE VIA CONTACTS FOR INTERCONNECT APPLICATIONS
App. No. 12/538,772
→
DUAL STRESS MEMORIZATION TECHNIQUE FOR CMOS APPLICATION
App. No. 12/538,110
→
FINFET STRUCTURE WITH MULTIPLY STRESSED GATE ELECTRODE
App. No. 12/505,894
→
CONTACT SCHEME FOR FINFET STRUCTURES WITH MULTIPLE FINS
App. No. 12/434,233
→
METHOD OF FORMING ELECTRODEPOSITED CONTACTS
App. No. 12/130,381
→
SPACERS FOR FINFETS (FIELD EFFECT TRANSISTORS)
App. No. 12/124,410
→
SEMICONDUCTOR TRANSISTORS WITH CONTACT HOLES CLOSE TO GATES
App. No. 12/052,855
→
REDUNDANT MICRO-LOOP STRUCTURE FOR USE IN AN INTEGRATED CIRCUIT PHYSICAL DESIGN PROCESS AND METHOD OF FORMING THE SAME
App. No. 12/045,374
→
FIN-TYPE FIELD EFFECT TRANSISTOR
App. No. 11/972,412
→
FIN-TYPE FIELD EFFECT TRANSISTOR
App. No. 11/955,579
→
DRY ETCHBACK OF INTERCONNECT CONTACTS
App. No. 11/946,922
→
ELECTRICAL INTERCONNECTION STRUCTURE FORMATION
App. No. 11/941,165
→
BRIDGED GATE FINFET
App. No. 11/933,571
→
SEMICONDUCTOR STRUCTURES INTEGRATING DAMASCENE-BODY FINFET'S AND PLANAR DEVICES ON A COMMON SUBSTRATE AND METHODS FOR FORMING SUCH SEMICONDUCTOR STRUCTURES
App. No. 11/927,780
→
TECHNIQUES FOR ENABLING MULTIPLE VT DEVICES USING HIGH-K METAL GATE STACKS
App. No. 11/927,964
→
MOSFETS COMPRISING SOURCE/DRAIN RECESSES WITH SLANTED SIDEWALL SURFACES, AND METHODS FOR FABRICATING THE SAME
App. No. 11/928,356
→
SEMICONDUCTOR STRUCTURES FOR LATCH-UP SUPPRESSION AND METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES
App. No. 11/927,135
→
SEMICONDUCTOR STRUCTURES INTEGRATING DAMASCENE-BODY FINFET'S AND PLANAR DEVICES ON A COMMON SUBSTRATE AND METHODS FOR FORMING SUCH SEMICONDUCTOR STRUCTURES
App. No. 11/927,110
→
INTERCONNECT STRUCTURE WITH A BARRIER-REDUNDANCY FEATURE
App. No. 11/925,161
→
STRUCTURE AND METHOD FOR FABRICATING SELF-ALIGNED METAL CONTACTS
App. No. 11/925,168
→
SEMICONDUCTOR FINFET STRUCTURES WITH ENCAPSULATED GATE ELECTRODES AND METHODS FOR FORMING SUCH SEMICONDUCTOR FINFET STRUCTURES
App. No. 11/923,717
→
WRAPPED GATE JUNCTION FIELD EFFECT TRANSISTOR
App. No. 11/875,190
→
DUAL METAL GATE FINFETS WITH SINGLE OR DUAL HIGH-K GATE DIELECTRIC
App. No. 11/860,840
→
METHOD OF FABRICATING ULTRA-DEEP VIAS AND THREE-DIMENSIONAL INTEGRATED CIRCUITS USING ULTRA-DEEP VIAS
App. No. 11/853,139
→
METHOD OF FABRICATING ULTRA-DEEP VIAS AND THREE-DIMENSIONAL INTEGRATED CIRCUITS USING ULTRA-DEEP VIAS
App. No. 11/853,118
→
STRUCTURE AND METHOD FOR PRODUCING MULTIPLE SIZE INTERCONNECTIONS
App. No. 11/847,776
→
MUGFET WITH OPTIMIZED FILL STRUCTURES
App. No. 11/846,825
→
FULLY SILICIDED METAL GATE SEMICONDUCTOR DEVICE STRUCTURE
App. No. 11/840,774
→
N-CHANNEL MOSFETS COMPRISING DUAL STRESSORS, AND METHODS FOR FORMING THE SAME
App. No. 11/840,795
→
FORMATION OF OXIDATION-RESISTANT SEED LAYER FOR INTERCONNECT APPLICATIONS
App. No. 11/839,260
→
SHAPES-BASED MIGRATION OF ALUMINUM DESIGNS TO COPPER DAMASCENE
App. No. 11/837,768
→
SHAPES-BASED MIGRATION OF ALUMINUM DESIGNS TO COPPER DAMASCENE
App. No. 11/837,723
→
SEMICONDUCTOR CHIPS WITH REDUCED STRESS FROM UNDERFILL AT EDGE OF CHIP
App. No. 11/830,228
→
BURIED METAL-SEMICONDUCTOR ALLOY LAYERS AND STRUCTURES AND METHODS FOR FABRICATION THEREOF
App. No. 11/828,455
→
METAL INTERCONNECT FORMING METHODS AND IC CHIP INCLUDING METAL INTERCONNECT
App. No. 11/770,928
→
SEMICONDUCTOR STRUCTURES FOR LATCH-UP SUPPRESSION AND METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES
App. No. 11/764,571
→
DUAL STRESS MEMORIZATION TECHNIQUE FOR CMOS APPLICATION
App. No. 11/758,291
→
FORMATION OF SPACERS FOR FINFETS (FIELD EFFECT TRANSISTORS)
App. No. 11/679,862
→
CONTACT FORMING METHOD AND RELATED SEMICONDUCTOR DEVICE
App. No. 11/668,717
→
FULLY SILICIDING REGIONS TO IMPROVE PERFORMANCE
App. No. 11/624,324
→
STRUCTURE AND METHOD FOR MOBILITY ENHANCED MOSFETS WITH UNALLOYED SILICIDE
App. No. 11/619,809
→
REDUNDANT MICRO-LOOP STRUCTURE FOR USE IN AN INTEGRATED CIRCUIT PHYSICAL DESIGN PROCESS AND METHOD OF FORMING THE SAME
App. No. 11/552,225
→
COPPER CONTACT VIA STRUCTURE USING HYBRID BARRIER LAYER
App. No. 11/465,865
→
MOSFETS COMPRISING SOURCE/DRAIN RECESSES WITH SLANTED SIDEWALL SURFACES, AND METHODS FOR FABRICATING THE SAME
App. No. 11/427,491
→
MULTI-BIT HIGH-DENSITY MEMORY DEVICE AND ARCHITECTURE AND METHOD OF FABRICATING MULTI-BIT HIGH-DENSITY MEMORY DEVICES
App. No. 11/427,487
→
N-CHANNEL MOSFETS COMPRISING DUAL STRESSORS, AND METHODS FOR FORMING THE SAME
App. No. 11/420,047
→
RELIABLE VIA CONTACT INTERCONNECT STRUCTURE
App. No. 11/435,410
→
STRUCTURE AND METHOD OF FORMING ELECTRODEPOSITED CONTACTS
App. No. 11/308,433
→
FORMATION OF OXIDATION-RESISTANT SEED LAYER FOR INTERCONNECT APPLICATIONS
App. No. 11/308,284
→
INTERCONNECT STRUCTURE WITH A BARRIER-REDUNDANCY FEATURE
App. No. 11/308,220
→
EXTENDED RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED CONTACT AREA AND METHOD FOR FORMING EXTENDED RAISED SOURCE/DRAIN STRUCTURE
App. No. 11/307,759
→
SEMICONDUCTOR STRUCTURES FOR LATCH-UP SUPPRESSION AND METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES
App. No. 11/340,737
→
INTEGRATED CIRCUIT STRUCTURES WITH SILICON GERMANIUM FILM INCORPORATED AS LOCAL INTERCONNECT AND/OR CONTACT
App. No. 11/275,481
→
FINFET STRUCTURE WITH MULTIPLY STRESSED GATE ELECTRODE
App. No. 11/164,621
→
PROCESS FOR FORMING A REDUNDANT STRUCTURE
App. No. 11/164,223
→
ELECTRICAL INTERCONNECTION STRUCTURE FORMATION
App. No. 11/164,107
→
SEMICONDUCTOR TRANSISTORS WITH CONTACT HOLES CLOSE TO GATES
App. No. 11/163,966
→
SHAPES-BASED MIGRATION OF ALUMINUM DESIGNS TO COPPER DAMASCENE
App. No. 11/256,025
→
METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES
App. No. 11/254,929
→
METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES
App. No. 11/254,934
→
SEMICONDUCTOR FINFET STRUCTURES WITH ENCAPSULATED GATE ELECTRODES AND METHODS FOR FORMING SUCH SEMICONDUCTOR FINFET STRUCTURES
App. No. 11/225,654
→
SEMICONDUCTOR STRUCTURES INTEGRATING DAMASCENE-BODY FINFET'S AND PLANAR DEVICES ON A COMMON SUBSTRATE AND METHODS FOR FORMING SUCH SEMICONDUCTOR STRUCTURES
App. No. 11/211,956
→
DRY ETCHBACK OF INTERCONNECT CONTACTS
App. No. 11/161,538
→
FIN-TYPE FIELD EFFECT TRANSISTOR
App. No. 11/161,442
→
FORMATION OF FULLY SILICIDED (FUSI) GATE USING A DUAL SILICIDE PROCESS
App. No. 11/195,994
→
STRUCTURE AND METHOD FOR PRODUCING MULTIPLE SIZE INTERCONNECTIONS
App. No. 11/160,669
→
FORMING OF LOCAL AND GLOBAL WIRING FOR SEMICONDUCTOR PRODUCT
App. No. 10/908,623
→
STABILIZATION OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HAFNIUM OXIDE BASED SILICON TRANSISTORS FOR CMOS
App. No. 11/118,521
→
USING METAL/METAL NITRIDE BILAYERS AS GATE ELECTRODES IN SELF-ALIGNED AGGRESSIVELY SCALED CMOS DEVICES
App. No. 11/111,592
→
VIA BARRIER LAYERS CONTINUOUS WITH METAL LINE BARRIER LAYERS AT NOTCHED OR DIELECTRIC MESA PORTIONS IN METAL LINES
App. No. 10/906,265
→
METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES
App. No. 10/904,884
→
SHAPES-BASED MIGRATION OF ALUMINUM DESIGNS TO COPPER DAMASCENE
App. No. 10/305,644
→