Metal interconnect and IC chip including metal interconnect
View Patent ↗A metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.
1. An integrated circuit (IC) chip comprising:
a middle-of-the-line (MOL) layer including a high dielectric constant (high-k) dielectric;
a first metal layer above and in direct physical contact with the MOL layer, the first metal layer including a low dielectric constant (low-k) dielectric; and
a metal interconnect including:
a contact having a first portion in the high-k dielectric of the MOL layer and a second portion in the low-k dielectric of the first metal layer, and
a wire coupled to the contact and positioned in the low-k dielectric of the first metal layer,
wherein the low-k dielectric of the first metal layer extends beyond a lower surface of a liner layer of the wire.
2. The IC chip of claim 1 , wherein the contact includes a material selected from the group consisting of: tungsten (W), copper (Cu) and aluminum (Al).
3. The IC chip of claim 1 , wherein the high-k dielectric includes a silicon dioxide (SiO2), and the low-k dielectric is selected from the group consisting of: a spin-on polymer, vapor deposited SiLK™, vapor deposited hydrogenated silicon oxycarbide (SiCOH) and organosilicates.
4. The IC chip of claim 1 , further comprising a back-end-of-line (BEOL) layer over the first metal layer and the metal interconnect.
5. The IC chip of claim 1 , wherein a portion of the low-k dielectric of the first metal layer is positioned between the high-k dielectric and the wire.
6. The IC chip of claim 1 , wherein the low-k dielectric has a dielectric constant value of less than approximately 3.9.
7. The IC chip of claim 6 , wherein the high-k dielectric has a dielectric constant value of greater than approximately 3.9.
8. An integrated circuit (IC) chip comprising:
a middle-of-the-line (MOL) layer including a high dielectric constant (high-k) dielectric;
a first metal layer above and in direct physical contact with the MOL layer, the first metal layer including a low dielectric constant (low-k) dielectric; and
a plurality of metal interconnects, each of the plurality of metal interconnects including:
a contact having a first portion in the high-k dielectric of the MOL layer and a second portion in the low-k dielectric of the first metal layer, and
a wire coupled to the contact and positioned in the low-k dielectric of the first metal layer,
wherein the low-k dielectric of the first metal layer extends beyond a lower surface of a liner layer of the wire of each of the plurality of metal interconnects, and wherein a portion of the low-k dielectric of the first metal layer is positioned between the high-k dielectric and the wire of each of the plurality of metal interconnects.
9. The IC chip of claim 8 , wherein the contact includes a material selected from the group consisting of: tungsten (W), copper (Cu) and aluminum (Al).
10. The IC chip of claim 8 , wherein the high-k dielectric includes a silicon dioxide (SiO2), and the low-k dielectric is selected from the group consisting of: a spin-on polymer, vapor deposited SiLK™, vapor deposited hydrogenated silicon oxycarbide (SiCOH) and organosilicates.
11. The IC chip of claim 8 , further comprising a back-end-of-line (BEOL) layer over the metal interconnect and the first metal layer.
12. The IC chip of claim 8 , wherein the low-k dielectric has a dielectric constant value of less than approximately 3.9.
13. The IC chip of claim 12 , wherein the high-k dielectric has a dielectric constant value of greater than approximately 3.9.
14. The IC chip of claim 8 , wherein the low-k dielectric of the first metal layer separates the plurality of metal interconnects.
15. An integrated circuit (IC) chip comprising:
a middle-of-the-line (MOL) layer including a high dielectric constant (high-k) dielectric, wherein the high-k dielectric includes a silicon dioxide (SiO2);
a first metal layer above and in direct physical contact with the MOL layer, the first metal layer including a low dielectric constant (low-k) dielectric, wherein the low-k dielectric is selected from the group consisting of: a spin-on polymer, vapor deposited SiLK™, vapor deposited hydrogenated silicon oxycarbide (SiCOH) and organosilicates; and
a metal interconnect including:
a contact having a first portion in the high-k dielectric of the MOL layer and a second portion in the low-k dielectric of the first metal layer, and
a wire coupled to the contact and positioned in the low-k dielectric of the first metal layer,
wherein the low-k dielectric of the first metal layer extends beyond a lower surface of a liner layer of the wire, and wherein a portion of the low-k dielectric of the first metal layer is positioned between the high-k dielectric and the wire of each of the plurality of metal interconnects.