finFET structure with multiply stressed gate electrode
View Patent ↗A semiconductor structure and its method of fabrication include a semiconductor fin located over a substrate. A gate electrode is located over the semiconductor fin. The gate electrode has a first stress in a first region located closer to the semiconductor fin and a second stress which is different than the first stress in a second region located further from the semiconductor fin. The semiconductor fin may also be aligned over a pedestal within the substrate. The semiconductor structure is annealed under desirable stress conditions to obtain an enhancement of semiconductor device performance.
1. A finFET structure comprising:
a semiconductor fin located over a substrate;
a gate dielectric located upon a sidewall of the semiconductor fin;
an inverted U shaped gate electrode located over and straddling the semiconductor fin and upon the gate dielectric, the inverted U shaped gate electrode having a first stress in a first conformal sub-layer region located nearer the semiconductor fin and a second stress which is different than the first stress in a second conformal sub-layer region located further from the semiconductor fin; and
a plurality of source and drain regions within the semiconductor fin at locations not covered by the inverted U shaped gate electrode.
2. The structure of claim 1 wherein the substrate is a semiconductor-on-insulator substrate.
3. The structure of claim 1 wherein the semiconductor fin comprises a semiconductor material selected from the group consisting of Si, SiC, SiGe, SiGeC, Ge, GaAs, InAs, InP, other III-V or II-VI compound semiconductor materials and organic semiconductor materials.
4. The structure of claim 1 wherein the first stress and the second stress provide a gradient of stress.
5. The structure of claim 1 wherein the first stress and the second stress are of opposite type.
6. The structure of claim 1 wherein the semiconductor fin is located over a pedestal within the substrate.
7. The structure of claim 1 wherein the semiconductor fin is located aligned over a pedestal within the substrate.
8. The structure of claim 1 further comprising a stress imparting layer located over the gate electrode.
9. The structure of claim 1 wherein the stress imparting layer has a third stress different than the second stress and the first stress.