Method for forming self-aligned dual salicide in CMOS technologies
View Patent ↗A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.
1. A method of forming metal silicide layers over a semiconductor substrate, said method comprising:
forming a first well region in said semiconductor substrate for accommodating a first type semiconductor device;
forming a second well region in said semiconductor substrate for accommodating a second type semiconductor device;
selectively forming a first metal layer over said second type semiconductor device;
depositing a capping layer over said first metal layer;
depositing a second metal layer over said capping layer and said first type semiconductor device; and
performing a salicide formation on the first and second type semiconductor devices.
2. The method of claim 1 , wherein said performing of said silicide formation on said first and second type semiconductor devices is accomplished by:
annealing the first and second metal layers;
removing said capping layer; and
removing un-reacted metal from said first and second type semiconductor devices.
3. The method of claim 1 , wherein said first well region is configured as a NFET (N-type field effect transistor) well region and said second well region is configured as a PFET (P-type field effect transistor) well region.
4. The method of claim 1 , wherein said first well region is configured as a PFET (P-type field effect transistor) well region and said second well region is configured as a NFET (N-type field effect transistor) well region.
5. The method of claim 1 , wherein said first metal layer is formed of different materials than said second metal layer.
6. The method of claim 1 , wherein said first type semiconductor device is formed by:
configuring an insulator layer over said first well region;
configuring a gate region over said insulator layer;
forming insulative spacers on opposite sides of said gate region; and
implanting source/drain regions in said first well region.
7. The method of claim 1 , wherein said second type semiconductor device is formed by:
configuring an insulator layer over said second well region;
configuring a gate region over said insulator layer;
forming insulative spacers on opposite sides of said gate region; and
implanting source/drain regions in said second well region.
8. The method of claim 1 , further comprising forming a second capping layer over said second metal layer prior to said performing of said salicide formation.
9. The method of claim 8 , wherein said capping layer and said second capping layer comprises any of TiN, Ti, and TaN.
10. The method of claim 1 , wherein said first metal layer and second metal layer comprises any of Ti, Co, Ni, Pt, Re, W, Pd, Ta, Nb, and their alloys.