Dry etchback of interconnect contacts
View Patent ↗A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tungsten contact after or during the M1 RIE process. The recessed contact is then subsequently metalized during the M1 liner/plating process. The tungsten contact height is reduced after it has been fully formed.
1. A method of making an electronic device comprising the steps of:
providing a substrate on which contacts are to be formed;
providing a conductive via comprised of a first conductive material formed in an oxide on said substrate;
providing a dielectric layer on said conductive via;
providing an oxide layer on said dielectric layer;
providing a photoresist layer on said oxide layer;
forming openings in said photoresist layer;
removing in said openings said dielectric layer and said oxide layer with a fluorocarbon containing gas;
removing said photoresist layer;
removing a portion of said first conductive material in said openings with a fluorine containing gas;
depositing a second conductive material in said openings to form a composite conductive via comprising said first conductive material and said second conductive material.
2. The method of claim 1 wherein said fluorine containing gas is selected from the group consisting of NF 3 , F 2 and SF 6 .
3. The method of claim 1 wherein said dielectric layer is a low-K SiCOH material.
4. The method of claim 3 wherein said low-K SiCOH material is a porous ultra low-K material.
5. The method of claim 1 wherein said first conductive material in Tungsten and said second conductive material is Copper.
6. The method of claim 2 wherein said fluorine containing gas removal comprises approximately 500 sccm of Argon and approximately 50 sccm of NF 3 .
7. The method of claim 6 wherein said fluorine containing gas removal further comprises approximately 10 sccm O 2 and 50 sccm of CH 2 F 2 or CH 3 F.
8. The method of claim 6 wherein said fluorine containing gas removal pressure is approximately 100 mTorr to approximately 200 mTorr.
9. A method of making an electronic device comprising the steps of:
providing a substrate on which contacts are to be formed;
providing a conductive via comprised of a first conductive material formed in an oxide on said substrate;
providing a dielectric layer on said conductive via;
providing an oxide layer on said dielectric layer;
providing a photoresist layer on said oxide layer;
forming openings in said photoresist layer;
removing in said openings said dielectric layer and said oxide layer with a fluorocarbon containing gas;
removing said photoresist layer and removing in said openings a portion of said first conductive material with a fluorine containing gas;
depositing a second conductive material in said openings to form a composite conductive via comprising said first conductive material and said second conductive material.
10. The method of claim 9 wherein said fluorine containing gas is selected from the group consisting of NF 3 , F 2 and SF 6 .
11. The method of claim 9 wherein said dielectric layer is a low-K SiCOH material.
12. The method of claim 11 wherein said low-K SiCOH material is a porous ultra low-K material.
13. The method of claim 9 wherein said first conductive material in Tungsten and said second conductive material is Copper.
14. The method of claim 10 wherein said fluorine containing gas removal comprises approximately 500 sccm of Argon and approximately 50 sccm of NF 3 .
15. The method of claim 14 wherein said fluorine containing gas removal further comprises approximately 10 sccm O 2 and 50 sccm of CH 2 F 2 or CH 3 F.
16. The method of claim 14 wherein said fluorine containing gas removal pressure is approximately 100 mTorr to approximately 200 mTorr.
17. An electronic device, comprising:
a poly-silicon gate formed on a substrate;
a composite stud via structure in contact with said poly-silicon gate, said composite stud via structure having a first portion and a second portion.
18. The electronic device of claim 17 wherein said first portion is comprised of Tungsten and said second portion is comprised of Copper.
19. The electronic device of claim 18 wherein only said first portion is in contact with said poly-silicon gate.
20. The electronic device of claim 19 wherein said composite stud via structure is approximately 100 nanometers in width and approximately 2,000 angstroms in height.
21. The electronic device of claim 19 wherein said first portion is approximately 500 angstroms in height.
22. The electronic device of claim 18 wherein said first portion is in contact with said poly-silicon gate and a conductive metal interconnect.