Dual stress memorization technique for CMOS application
View Patent ↗A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed.
1. A semiconductor structure comprising:
at least one p-type field effect transistor (PFET) and at least one n-type field effect transistor (NFET) located on a semiconductor substrate;
a stress-transmitting dielectric layer surrounding said at least one PFET and said at least one NFET;
a tensile stress generating film located directly on an upper surface of said stress-transmitting dielectric layer and only overlying an area of said at least one NFET;
a compressive stress generating film located directly on an upper surface of said stress-transmitting dielectric layer and only overlying an area of said at least one PFET; and
an encapsulating dielectric film located atop said compressive stress generating film and said tensile stress generating film.
2. The semiconductor structure of claim 1 , wherein said compressive stress generating film comprises a refractory metal nitride.
3. The semiconductor structure of claim 2 , wherein said refractory metal nitride is selected from the group consisting of TaN, TiN, WN, MoN, NbN, ReN, and a combination thereof.
4. The semiconductor structure of claim 3 , wherein said refractory metal nitride is TiN.
5. The semiconductor structure of claim 1 , wherein said compressive stress generating film applies a compressive stress from about 5 GPa to about 20 GPa in magnitude to at least one channel of said at least one PFET.
6. The semiconductor structure of claim 1 , wherein said stress-transmitting dielectric layer is a silicon oxide and said encapsulating dielectric film is selected from the group consisting of a silicon oxide and a silicon nitride.