Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
View Patent ↗Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.
1. A method of making a semiconductor structure, the method comprising:
etching a trench in a mask covering a substrate;
forming a first epitaxial layer in the trench;
implanting ions into the first epitaxial layer through the mask such that the trench self-aligns the implanted ions with the first epitaxial layer;
transforming the implanted ions into a buried isolation region electrically isolating the first epitaxial layer from the substrate; and
forming a second epitaxial layer in the trench and on the first epitaxial layer.
2. The method of claim 1 wherein the first epitaxial layer and the substrate include silicon, and the buried isolation region includes oxygen and silicon, and implanting ions into the first epitaxial layer further comprises:
implanting oxygen-containing ions into the epitaxial layer.
3. The method of claim 1 wherein an interface is defined between the epitaxial layer and the substrate, and implanting ions into the first epitaxial layer further comprises:
selecting an ion energy such that an ion range is near the interface.
4. The method of claim 1 wherein the substrate is moncrystalline and the trench extends to the substrate, and forming the first epitaxial layer further comprises:
using the substrate as a seed for forming the first epitaxial layer.
5. The method of claim 1 wherein forming the second epitaxial layer further comprises:
using the first epitaxial layer as a seed for forming the second epitaxial layer.
6. The method of claim 1 wherein the implanted ions are transformed by a thermal treatment into the buried isolation region.
7. The method of claim 1 wherein the thermal heat treatment anneals damage in the first epitaxial layer resulting from the ion implantation, and further comprising:
using the first epitaxial layer as a seed for forming the second epitaxial layer.
8. A method of making a semiconductor structure, the method comprising:
forming a semiconductor fin projecting from a substrate;
etching portions of the substrate surrounding the semiconductor fin to define a recess in the substrate about a base of the semiconductor fin; and
at least partially filling the recess with a dielectric material to electrically isolate the semiconductor fin from the substrate,
wherein the semiconductor fin is formed by a damascene process, and a patterned mask used to form the semiconductor fin is removed before etching portions of the substrate surrounding the semiconductor fin.
9. The method of claim 8 further comprising:
forming a sidewall spacer on at least one sidewall of the semiconductor fin before etching portions of the substrate surrounding the semiconductor fin.
10. The method of claim 9 further comprising:
removing the sidewall spacer from the semiconductor fin after etching portions of the substrate surrounding the semiconductor fin.
11. The method of claim 8 further comprising:
forming a protective cap on the semiconductor fin before etching portions of the substrate surrounding the semiconductor fin.
12. The method of claim 8 wherein an insulating layer separates the semiconductor fin from the substrate, and the dielectric material fills the recess to a height above the insulating layer.
13. The method of claim 8 wherein the semiconductor fin includes a channel region, and further comprising:
doping the channel region; and
forming a gate dielectric on the first and second sidewalls of the semiconductor fin before filling the regions adjacent the fin with a conductor.
14. The method of claim 13 further comprising:
patterning and etching the conductor to form a first gate adjacent a first sidewall of the channel region; and
forming a second gate adjacent a second sidewall of the channel region, the first gate being electrically isolated from the second gate.