Metal interconnect forming methods and IC chip including metal interconnect

1. A method of forming a metal interconnect, the method comprising:

providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric;

recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric;

forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric;

forming a planarizing layer over the second dielectric, wherein the planarizing layer forming includes:

forming a non-photoactive polymer layer; and

forming a low temperature oxide (LTO) layer over the non-photoactive polymer layer;

forming an opening through the planarizing layer and into the second dielectric to the contact; and

forming a metal in the opening to form the metal interconnect.

2. The method of claim 1 , wherein the contact includes a material selected from the group consisting of: tungsten (W), copper (Cu) and aluminum (Al).

3. The method of claim 1 , wherein the first dielectric includes a silicon dioxide (SiO 2 ), and the second dielectric is selected from the group consisting of: a spin-on polymer, vapor deposited SiLK™, vapor deposited hydrogenated silicon oxycarbide (SiCOH) and organosilicates.

4. The method of claim 1 , wherein the opening forming includes:

patterning a mask;

first etching to open the LTO layer; and

second etching the planarizing layer and the second dielectric at substantially the same rate.

5. The method of claim 4 , wherein the second etching includes using fluorocarbon and oxygen based chemistries.

6. The method of claim 4 , wherein the second etching is timed to only reach a surface of the contact.

7. The method of claim 1 , wherein the recessing of the first dielectric prevents overetching during the opening forming.

8. The method of claim 1 , further comprising forming a back-end-of line layer over the metal interconnect.

9. A method of forming a metal interconnect, the method comprising:

providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a high dielectric constant (high-k) dielectric;

recessing the high-k dielectric such that the contact extends beyond an upper surface of the high-k dielectric;

forming a low dielectric constant (low-k) dielectric over the high-k dielectric such that the low-k dielectric surrounds at least a portion of the contact;

forming a planarizing layer over the low-k dielectric by forming a non-photoactive polymer layer over the low-k dielectric and a low temperature oxide (LTO) layer over the non-photoactive polymer layer;

forming an opening through the planarizing layer and into the low-k dielectric to the contact by first etching to open the LTO layer and second etching the planarizing layer and the low-k dielectric at substantially the same rate; and

forming a metal in the opening to form the metal interconnect.

10. The method of claim 9 , wherein the contact includes a material selected from the group consisting of: tungsten (W), copper (Cu) and aluminum (Al).

11. The method of claim 9 , wherein the high-k dielectric includes a silicon dioxide (SiO 2 ), and the low-k dielectric is selected from the group consisting of: a spin-on polymer, vapor deposited SiLK™ vapor deposited hydrogenated silicon oxycarbide (SiCOH) and organosilicates.

12. The method of claim 9 , wherein the second etching includes using fluorocarbon and oxygen based chemistries.

13. The method of claim 9 , wherein the second etching is timed to only reach a surface of the contact.

14. The method of claim 9 , wherein the recessing of the first dielectric prevents overetching during the opening forming.

15. The method of claim 9 , further comprising forming a back-end-of-line layer over the metal interconnect.