Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures
View Patent ↗Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.
1. A semiconductor structure comprising:
a substrate of a semiconductor material having a top surface;
a first doped well formed in the semiconductor material of the substrate;
a second doped well formed in the semiconductor material of the substrate and disposed adjacent to the first doped well; and
a dielectric-filled trench defined in the substrate between the first and second doped wells, the trench including a base, first sidewalls intersecting the top surface, and second sidewalls disposed between the base and the first sidewalls, the second sidewalls having a wider separation than the first sidewalls.
2. The semiconductor structure of claim 1 wherein the first doped well has a first conductivity type and the second doped well has a second conductivity type, and further comprising:
a first field effect transistor with source and drain regions in the first doped well; and
a second field effect transistor with source and drain regions in the second doped well, the wider separation of the second sidewalls operating to reduce latch-up of the first and second field effect transistors.
3. The semiconductor structure of claim 2 wherein the dielectric-filled trench defines a shallow trench isolation region between the first and second doped wells.
4. The semiconductor structure of claim 1 wherein the semiconductor material of the substrate is monocrystalline, and the semiconductor material of the substrate bordering the second sidewalls and the base includes a damage region of non-monocrystalline semiconductor material.
5. The semiconductor structure of claim 1 wherein the first doped well and the second doped well have a first conductivity type, and further comprising:
a third doped well formed in the semiconductor material of the substrate, the third doped well arranged between the first doped well and the top surface, the third doped well having a second conductivity type that differs from the first conductivity type.
6. The semiconductor structure of claim 5 further comprising:
a first field effect transistor with source and drain regions in the first doped well; and
a second field effect transistor with source and drain regions in the third doped well, the wider separation of the second sidewalls operating to reduce latch-up of the first and second field effect transistors.
7. The semiconductor structure of claim 6 wherein the first and second doped wells have an n-type conductivity, the third doped well has a p-type conductivity, the source and drain regions of the first field effect transistor comprises p-type diffusions, and the source and drain regions of the second field effect transistor comprise n-type diffusions.
8. The semiconductor structure of claim 1 wherein the dielectric-filled trench defines a shallow trench isolation region between the first and second doped wells.
9. The semiconductor structure of claim 1 wherein the dielectric-filled trench is filled by a dielectric material containing silicon and oxygen.
10. The semiconductor structure of claim 1 wherein the first doped well has a first conductivity type and the second doped well has a second conductivity type opposite to the first conductivity type.