Semiconductor transistors with contact holes close to gates

1. A structure formation method, comprising:

providing a structure including:

(a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) regions, wherein the channel region is disposed between and electrically coupled to the first and second S/D regions,

(b) a gate dielectric region in direct physical contact with the channel region via an interfacing surface which defines a reference direction perpendicular to the interfacing surface, wherein the gate dielectric region is above the channel region in the reference direction,

(c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region, and

(d) a hard cap region on the gate region;

forming a protection umbrella region from the hard cap region such that the gate region is completely in a shadow of the protection umbrella region, wherein the shadow of the protection umbrella region comprises a space shielded by the protection umbrella region from an imaginary light point source (i) directly above the protection umbrella region in the reference direction and (ii) infinitely far from the protection umbrella region;

blanket depositing an inter-level dielectric (ILD) layer on the structure after said forming the protection umbrella region is performed;

creating a contact hole in the ILD layer directly above the second S/D region and aligned with an edge of the protection umbrella region, wherein the contact hole is physically isolated from the gate region by the ILD layer; and

filling the contact hole with an electrically conducting material,

wherein the protection umbrella region comprises silicon dioxide, and

wherein the ILD layer comprises a low-K dielectric material, wherein K <3.5.

2. A structure formation method, comprising:

providing a structure including:

(a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) regions, wherein the channel region is disposed between and electrically coupled to the first and second S/D regions,

(b) a gate dielectric region in direct physical contact with the channel region via an interfacing surface which defines a reference direction perpendicular to the interfacing surface, wherein the gate dielectric region is above the channel region in the reference direction,

(c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region, and

(d) a hard cap region on the gate region;

forming a protection umbrella region from the hard cap region such that the gate region is completely in a shadow of the protection umbrella region, wherein the shadow of the protection umbrella region comprises a space shielded by the protection umbrella region from an imaginary light point source (i) directly above the protection umbrella region in the reference direction and (ii) infinitely far from the protection umbrella region;

blanket depositing an inter-level dielectric (ILD) layer on the structure after said forming the protection umbrella region is performed;

creating a contact hole in the ILD layer directly above the second S/D region and aligned with an edge of the protection umbrella region, wherein the contact hole is physically isolated from the gate region by the ILD layer; and

filling the contact hole with an electrically conducting material,

wherein said forming the protection umbrella region from the hard cap region comprises selectively depositing a dielectric material on only the hard cap region,

wherein the hard cap region comprises silicon dioxide, and

wherein the dielectric material comprises silicon dioxide.

3. A structure formation method, comprising:

providing a structure including:

(a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) regions, wherein the channel region is disposed between and electrically coupled to the first and second S/D regions,

(b) a gate dielectric region in direct physical contact with the channel region via an interfacing surface which defines a reference direction perpendicular to the interfacing surface, wherein the gate dielectric region is above the channel region in the reference direction,

(c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region, and

(d) a hard cap region on the gate region;

forming a protection umbrella region from the hard cap region such that the gate region is completely in a shadow of the protection umbrella region, wherein the shadow of the protection umbrella region comprises a space shielded by the protection umbrella region from an imaginary light point source (i) directly above the protection umbrella region in the reference direction and (ii) infinitely far from the protection umbrella region;

blanket depositing an inter-level dielectric (ILD) layer on the structure after said forming the protection umbrella region is performed;

creating a contact hole in the ILD layer directly above the second S/D region and aligned with an edge of the protection umbrella region, wherein the contact hole is physically isolated from the gate region by the ILD layer; and

filling the contact hole with an electrically conducting material,

wherein said creating the contact hole comprises etching the ILD layer using a blocking mask including the protection umbrella region, and

wherein said etching the ILD layer comprises:

forming an oxide layer on the ILD layer;

creating an opening in the oxide layer; and

etching the ILD layer through the opening using the oxide layer and the protection umbrella region as the blocking mask.

4. A structure formation method, comprising:

providing a structure including:

(a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) regions, wherein the channel region is disposed between and electrically coupled to the first and second S/D regions,

(b) a gate dielectric region in direct physical contact with the channel region via an interfacing surface which defines a reference direction perpendicular to the interfacing surface, wherein the gate dielectric region is above the channel region in the reference direction,

(c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region, and wherein the gate region comprises (i) a polysilicon region on and in direct physical contact with the gate dielectric region and (ii) first and second gate silicide regions on first and second sidewalls of the polysilicon region, respectively;

(d) a hard cap region on the gate region; forming a protection umbrella region from the hard cap region such that the gate region is completely in a shadow of the protection umbrella region, wherein the shadow of the protection umbrella region comprises a space shielded by the protection umbrella region from an imaginary light point source (i) directly above the protection umbrella region in the reference direction and (ii) infinitely far from the protection umbrella region;

blanket depositing an inter-level dielectric (ILD) layer on the structure after said forming the protection umbrella region is performed;

creating a contact hole in the ILD layer directly above the second S/D region and aligned with an edge of the protection umbrella region, wherein the contact hole is physically isolated from the gate region by the ILD layer, and wherein said creating the contact hole comprises (i) forming an oxide layer on the ILD layer, (ii) creating an opening in the oxide layer, and, (ii) etching the ILD layer through the opening using the oxide layer and the protection umbrella region as a blocking mask; and

filling the contact hole with an electrically conducting material.

5. The method of claim 4 ,

wherein the protection umbrella region comprises silicon dioxide, and

wherein the ILD layer comprises a low-K dielectric material, wherein K <3.5.

6. The method of claim 4 , wherein the electrically conducting material comprises tungsten.

7. The method of claim 4 , wherein said forming the protection umbrella region from the hard cap region comprises selectively depositing a dielectric material on only the hard cap region.