Chip package structure and chip packaging process
A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a chip is disposed on the first encapsulant and the chip is electrically connected to the circuit substrate. Finally, a compound is deposited over the first encapsulant and the chip to form a chip package. The chip package is warp resistant and the chip packaging process increases overall production yield.
1. A chip package structure, comprising:
a heat sink having a cavity;
a circuit substrate having a top surface disposed on the heat sink, wherein the circuit substrate has an opening that corresponds in position to the cavity;
a chip disposed at a bottom of the cavity, wherein the chip is electrically connected to the circuit substrate;
a first encapsulant disposed between a bottom surface of the chip and the heat sink, wherein the first encapsulant is in contact with the sidewalls of the cavity;
a second encapsulant disposed over the first encapsulant to encapsulate the chip and a portion of the circuit substrate; and
a plurality of conductive bumps disposed on the top surface of the circuit substrate outside the second encapsulant.
2. The chip package structure of claim 1 , wherein the first encapsulant has a height smaller than the depth of the cavity.
3. The chip package structure of claim 1 , wherein the first encapsulant has a height equal to the depth of the cavity.
4. The chip package structure of claim 1 , wherein the first encapsulant has a height greater than the depth of the cavity.
5. The chip package structure of claim 1 , further comprising a heat-conductive interlayer, wherein the heat-conductive interlayer is disposed between the chip and the first encapsulant and extends between the circuit substrate and the heat sink.
6. The chip package structure of claim 5 , wherein the heat-conductive interlayer is a metallic layer.
7. The chip package structure of claim 5 , wherein the heat-conductive interlayer is a patterned metallic layer.
8. The chip package structure of claim 1 , further comprising a plurality of conductive wires for electrically connecting the chip and the circuit substrate, wherein the second encapsulant further encapsulates the conductive wires.
9. The chip package structure of claim 1 , wherein the first encapsulant and the second encapsulant are identical in material.
10. The chip package structure of claim 1 , wherein a material of the first encapsulant comprises epoxy resin.
11. The chip package structure of claim 1 , wherein the material of the second encapsulant comprises epoxy resin.
12. A chip package structure, comprising:
a heat sink having a cavity, wherein the cavity has a depth;
a circuit substrate disposed on the heat sink, wherein the circuit substrate has a top surface and an opening in a position that corresponds to the cavity;
a first encapsulant, disposed on the heat sink inside the cavity;
a chip disposed on the first encapsulant inside the cavity, wherein a thickness of the first encapsulant is at least one half of the depth of the cavity;
a plurality of conductive wires electrically connecting the chip and the circuit substrate;
a second encapsulant with the first encapsulant encapsulating the chip and the conductive wires, and at least the first encapsulant having contact with the bottom and the sidewalls of the cavity; and
a plurality of conductive bumps disposed on the top surface of the circuit substrate.
13. The chip package structure of claim 1 , wherein the cavity has a depth and a thickness of the first encapsulant is at least one half of the depth of the cavity.