Method for manufacturing anti-punch through semiconductor device
View Patent ↗A method for manufacturing an anti-punch through semiconductor device is described. The method is applied to a substrate having a plurality of device isolation structures in parallel arrangements and the upper surface of the device isolation structures is protruded from the surface of the substrate. A plurality of conductive layers in parallel arrangement is formed on the substrate and crosses the device isolation structures. A plurality of trench devices is formed between device isolation structures under the conductive layers. Each trench device includes a first conductive doping region at the bottom of the trench. The method further includes forming spacers on the sidewalls of the device isolation structures and the conductive layers. A dopant implant process is then performed by using the spacers as a mask to form a second conductive doping region between adjacent first conductive doping regions.
1. A method for fabricating an anti-punch through semiconductor device, applicable on a substrate, the method comprising:
forming a plurality of parallel arranged device isolation structures in the substrate for defining a plurality of active regions, wherein the device isolation structures are protruded from a surface of the substrate;
forming a plurality of parallel arranged conductive layers on the substrate, wherein the conductive layers cross the device isolation structures;
forming a plurality of trench devices in the active region between every two isolation structures underneath the conductive layers, wherein each trench device includes a first conductive type doped region disposed at a bottom of the trench device;
forming spacers on sidewalls of the device isolation structures and the conductive layer; and
performing a dopant implantation process to form a second conductive type doped region between every two neighboring first conductive type doped regions using the spacers as a mask.
2. The method of claim 1 , wherein the step of forming the spacers comprises:
forming an insulation material layer on the substrate; and
performing an anisotropic etching process to remove a portion of the insulation material layer.
3. The method of claim 1 , wherein the spacers are formed with a material comprising silicon nitride.
4. The method of claim 1 , wherein a boundary of the second conductive type doped region is adjusted according to a thickness of the spacer.
5. The method of claim 1 , wherein the first conductive type doped region is a P-type doped region and the second conductive type doped region is an N-type doped region.
6. The method of claim 1 , wherein the first conductive type doped region is an N-type doped region and the second conductive type doped region is a P-type doped region.
7. The method of claim 1 , wherein the trench device comprises a trench type memory device.
8. The method of claim 1 , wherein the trench device comprises a trench type capacitor.
9. The method of claim 1 , wherein the trench device comprises a trench type transistor.