IP Library Granted Patent US 7,244,679
Granted Patent B2
US 7,244,679 · App. 10/914,994 · Granted Jul 17, 2007

Methods of forming silicon quantum dots and methods of fabricating semiconductor memory devices using the same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,244,679
App. No.
10/914,994
Granted
Jul 17, 2007
Kind
B2
Abstract

Techiques for forming a silicon quantum dot, which can be applied to the formation of a semiconductor memory device, are disclosed. The techniques may include depositing a first dielectric layer on a semiconductor substrate, depositing a polysilicon layer on the first dielectric layer, forming a plurality of metal clusters on the polysilicon layer in regular distance, and etching the polysilicon layer using the plurality of metal clusters as a mask. As disclosed herein, it is possible to form the silicon quantum dots having the fineness and uniformity characteristic together with the single crystalline level characteristic.

Claims (12)

1. A method for fabricating a semiconductor memory device comprising:

defining an active region and non-active region using a device isolation layer formed on a semiconductor substrate;

depositing a first dielectric layer on the active region;

depositing a polysilicon layer on the first dielectric layer;

forming a plurality of metal clusters on the polysilicon layer;

forming separated silicon quantum dots by etching the polysilicon layer using the plurality of metal clusters at regular intervals as a mask until a top surface of the first dielectric layer is exposed;

removing the plurality of metal clusters;

depositing a second dielectric layer on the separated silicon quantum dots;

forming a conductive layer for gate electrodes on the second electric layer; and

removing the conductive layer and the first and second dielectric layers selectively.

2. The method as defined by claim 1 wherein each of the plurality of metal clusters comprises gold, silver, or a transition metal.

3. The method as defined by claim 1 wherein the polysilicon layer has a thickness in the range of 10 to 100 nanometers.

Assignments (10)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE LTD.
Reel/Frame 057336/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: MARVELL TECHNOLOGY CAYMAN I
To: CAVIUM INTERNATIONAL
Reel/Frame 057279/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: INPHI CORPORATION
To: MARVELL TECHNOLOGY CAYMAN I
Reel/Frame 056649/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2017
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 041373/0592 →
CORRECTIVE ASSIGNMENT TO CORRECT REMOVE PATENT NO. 878209 FROM EXHIBIT B PREVIOUSLY RECORDED AT REEL: 034009 FRAME: 0157. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 24, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034087/0097 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034009/0157 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR PREVIOUSLY RECORDED ON REEL 017749 FRAME 0335. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNOR SHOULD BE "DONGBUANAM SEMICONDUCTOR INC.". Recorded Jun 21, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017821/0670 →
CHANGE OF NAME Recorded Jun 8, 2006
From: DONGANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017749/0335 →
MERGER Recorded May 31, 2005
From: ANAM SEMICONDUCTOR INC.; ANAM SEMICONDUCTOR INC.
To: DONGBUANAM SEMICONDUCTOR, INC., A KOREAN CORPORATION
Reel/Frame 016593/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2004
From: KOH, KWAN-JU
To: ANAM SEMICONDUCTOR INC.
Reel/Frame 015677/0907 →