Test structure for characterizing junction leakage current
View Patent ↗For characterizing bulk leakage current of a junction, a center junction surrounded by an isolation structure is formed with a first depth. In addition, at least one periphery junction having a second depth greater than the first depth is formed in a portion of the center junction adjacent the isolation structure. A junction silicide is formed with the center and periphery junctions. The magnitude of a reverse-bias voltage across the junction silicide and the P-well is incremented for determining a critical magnitude of the reverse-bias when current through the junction silicide and the P-well reaches a threshold current density.
1. A method of characterizing leakage current of a junction, comprising:
forming a center junction having a first depth and being surrounded by an isolation structure;
forming at least one periphery junction having a second depth greater than the first depth in a portion of the center junction adjacent the isolation structure; and
forming the center and periphery junctions to abut a P-well that is uniformly doped under the center and periphery junctions.
2. The method of claim 1 , further comprising:
forming a junction silicide with the center and periphery junctions.
3. A method of characterizing leakage current of a junction, comprising:
forming a center junction having a first depth and being surrounded by an isolation structure;
forming at least one periphery junction having a second depth greater than the first depth in a portion of the center junction adjacent the isolation structure;
forming a junction silicide with the center and periphery junctions;
forming the center and periphery junctions in a P-well;
incrementing a magnitude of a reverse-bias across the junction silicide and the P-well; and
determining a critical magnitude of the reverse-bias when current through the junction silicide and the P-well reaches a threshold current density.
4. The method of claim 1 , wherein the center and periphery junctions have N-type conductivity.
5. The method of claim 1 , wherein formation of the center junction includes:
implanting a core dopant into the center junction; and
implanting a drain side dopant into the center junction.
6. The method of claim 5 , wherein the implantations of the core and drain side dopants are performed also for forming drain bit line junctions of a flash memory device.
7. The method of claim 1 , wherein formation of the periphery junction includes:
implanting a periphery dopant into the periphery junction.
8. The method of claim 7 , wherein formation of the periphery junction further includes:
implanting a co-implant dopant into the periphery junction.
9. The method of claim 8 , wherein implantations of the periphery and co-implant dopants are performed also for forming a source and a drain of a field effect transistor in a periphery region of a flash memory device.
10. The method of claim 1 , wherein the center and periphery junctions are formed within scribe lines of a semiconductor substrate having a flash memory device fabricated thereon.
11. A test system for characterizing leakage current for a junction, comprising:
a center junction formed to have a first depth and to be surrounded by an isolation structure;
at least one periphery junction formed to have a second depth greater than the first depth in a portion of the center junction adjacent the isolation structure; and
a P-well containing the center and periphery junctions with the P-well being uniformly doped in abutting the center and periphery junctions.
12. The test system of claim 11 , further comprising:
a junction silicide formed with the center and periphery junctions.
13. The test system of claim 12 , further comprising:
means for incrementing a magnitude of a reverse-bias across the junction silicide and the P-well to determine a critical magnitude of the reverse-bias when current through the junction silicide and the P-well reaches a threshold current density.
14. The test system of claim 11 , wherein the center and periphery junctions have N-type conductivity.
15. The test system of claim 11 , wherein the center junction comprises:
a core dopant implanted into the center junction; and
a drain side dopant implanted into the center junction.
16. The test system of claim 15 , wherein the core and drain side dopants also comprise bit line junctions of flash memory cells of a flash memory device within a semiconductor substrate having the center and periphery junctions and the flash memory device fabricated thereon.
17. The test system of claim 11 , wherein the periphery junction includes:
a periphery dopant implanted into the periphery junction.
18. The test system of claim 17 , wherein the periphery junction further includes:
a co-implant dopant implanted into the periphery junction.
19. The test system of claim 18 , wherein the periphery and co-implant dopants also comprise a source and a drain of a field effect transistor in a periphery region of a flash memory device.
20. The test system of claim 11 , wherein the center and periphery junctions are formed within scribe lines of a semiconductor substrate having a flash memory device fabricated thereon.