Method for fabricating a semiconductor device having salicide
View Patent ↗The present invention can protect from degradation of product reliability of a semiconductor caused during formation of a salicide suppression layer. In order to achieve this, unlike the conventional method in which the sidewall spacer of the gate electrode and the salicide suppression layer in the non-salicide region are formed through two etching processes, the salicide suppression layer and the sidewall spacer are formed at the same time with one etching process after the salicide suppression substance and the sidewall spacer substance are sequentially formed in the present invention, such that it is possible to efficiently prevent an undercut effect from occurring at the spacer side during the etching process for forming the salicide suppression layer, and to effectively prevent the surface of the semiconductor substrate from being damaged.
1. A method for fabricating a semiconductor device, comprising:
a. depositing a dielectric film spacer substance on an entire surface of the semiconductor substrate, said semiconductor substrate further comprising a salicide region and a non-salicide region, a gate oxide and a gate electrode on said semiconductor substrate in each of said salicide and non-salicide regions, and low concentration impurity regions in said semiconductor substrate adjacent said gate electrode;
b. forming an etch protection layer in said non-salicide region;
c. in the salicide region, etching the dielectric spacer substance to form a spacer on a sidewall of the gate electrode;
d. removing the etch protection layer to form a salicide suppression layer comprising the dielectric film spacer substance;
e. forming a metal salicide in the salicide region using a thermal annealing process; and thereafter
f. forming one or more implants in said non-salicide region.
2. The method of claim 1 , wherein the dielectric spacer substance comprises a first dielectric spacer layer and a second dielectric spacer layer thereon.
3. The method of claim 1 , wherein the dielectric spacer substance comprises a nitride film.
4. The method of claim 2 , wherein the first dielectric spacer layer differs from the second dielectric spacer layer.
5. The method of claim 1 , wherein the dielectric spacer substance is formed at a thickness of approximately 1000 Å.
6. The method of claim 4 , wherein the dielectric spacer substance is formed at a thickness of approximately 1000 Å.
7. The method of claim 2 , wherein the first spacer layer is formed in a thickness range of approximately 100–350 Å, and the second dielectric spacer layer is formed in a thickness range of approximately 650–900 Å.
8. The method of claim 4 , wherein the first spacer substance is formed in a thickness range of approximately 100–350 Å, and the second dielectric spacer substance is formed in a thickness range of approximately 650–900 Å.
9. The method of claim 7 , wherein the first dielectric spacer substance is formed in a temperature range of approximately 650–730° C., and the second dielectric spacer substance is formed in a temperature range of approximately 700–800° C.
10. The method of claim 2 , wherein the first dielectric spacer substance is formed in a temperature range of approximately 650–730° C., and the second dielectric spacer substance is formed in a temperature range of approximately 700–800° C.
11. The method of claim 1 , further comprising forming said gate oxide and said gate electrode on said semiconductor substrate.
12. The method of claim 9 , wherein said gate oxide consists essentially of silicon dioxide.
13. The method of claim 1 , further comprising forming said low concentration impurity region(s) in the semiconductor substrate by ion injection using the gate electrode as a mask.
14. The method of claim 2 , wherein one of the first dielectric spacer layer and the second dielectric spacer layer comprises one of a nitride film or silicon dioxide, and the other of the first dielectric spacer layer and the second dielectric spacer layer comprises the other of said nitride film or said silicon dioxide.
15. The method of claim 1 , wherein the etch protection layer comprises a photosensitive film.
16. The method of claim 1 , further comprising blanket depositing a metal substance over said semiconductor substrate prior to said thermal annealing process.
17. The method of claim 1 , wherein the dielectric spacer substance is formed at a thickness of approximately 1000 Å or less.
18. The method of claim 3 , wherein the dielectric spacer substance is formed at a thickness of approximately 1000 Å or less.
19. The method of claim 1 , wherein the gate oxide, the gate electrode, and the low concentration impurity regions in said non-salicide region are part of an ESD protection circuit.
20. The method of claim 1 , wherein said thermal annealing process comprises fast or rapid thermal annealing.
21. The method of claim 1 , further comprising the step of forming, before said metal salicide forming step, source/drain terminals in and/or on said salicide region using said gate electrode and said spacer as a mask.