Masked spacer etching for imagers
The invention relates to a dual masked spacer etch for improved dark current performance in imagers. After deposition of spacer material such as oxide, N-channel regions are first opened for N + source/drain implant and P-channel regions are then opened for P + source/drain implant. Prior to the N + source/drain implant, the wafer receives a patterned first spacer etch. During this first spacer etch, the photosensor region is covered with resist. Prior to the P + source/drain implant, a masked second spacer etch is performed. Again the photosensor region is protected with photoresist. In such a manner, spacers are formed on the gates of both the N-channel and P-channel transistors but in the photodiode region the spacer insulator remains.
1. An imaging array comprising:
at least one pixel comprising:
a photosensitive region;
a gate structure;
a continuous layer of an insulating material formed over the photosensitive region;
a spacer of the insulating material formed on at least one side of the gate structure; and
a layer of insulating material formed over said continuous layer of insulating material, said gate structure and said spacer.
2. The imaging array of claim 1 , wherein the pixel is part of a CMOS imager.
3. The imaging array of claim 1 , wherein said gate structure is a transfer gate.
4. The imaging array of claim 1 , wherein said gate structure is a reset gate.
5. The imaging array of claim 1 , wherein said gate structure is a source follower gate.
6. An integrated circuit with an imaging array comprising:
at least one pixel comprising:
a photosensitive region;
a gate structure;
a continuous layer of an insulating material formed over the photosensitive region;
a spacer of the insulating material formed on at least one side of the gate structure;
a peripheral circuit, said peripheral circuit having at least one transistor with a second gate structure and a second spacer of the insulating material formed on at least one side of the second gate structure; and
a layer of insulating material formed over said continuous layer of insulating material, said gate structure, said spacer and said peripheral circuit.
7. The integrated circuit of claim 6 , wherein the pixel is part of a CMOS imager.
8. The integrated circuit of claim 6 , wherein said gate structure is a source follower gate.
9. The integrated circuit of claim 6 , wherein said gate structure is a reset gate.
10. The integrated circuit of claim 6 , wherein said gate structure is a transfer gate.
11. The integrated circuit of claim 6 , wherein said gate structure is a row select gate.
12. The integrated circuit of claim 6 , wherein said second gate structure is a source follower gate.
13. The integrated circuit of claim 6 , wherein said second gate structure is a reset gate.
14. The integrated circuit of claim 6 , wherein said second gate structure is a transfer gate.
15. The integrated circuit of claim 6 , wherein said second gate structure is a row select gate.
16. An imager system, comprising:
a processor; and
an integrated circuit connected to provide signals to said processor, said integrated circuit comprising:
a pixel array which comprises a plurality of pixels, at least one said pixel of said pixel array comprising:
a photosensitive region;
at least one gate structure;
a layer of an insulating material over the photosensitive region; and
a spacer of the insulating material formed on at least one side of at least one gate structure; and
a peripheral circuit, said peripheral circuit having at least one transistor with a second gate structure having a second spacer of the insulating material formed on at least one side of the second gate structure.
17. An imaging array comprising:
at least one pixel comprising:
a photosensitive region;
a gate structure for a row select gate;
a layer of an insulating material formed over the photosensitive region; and
a spacer of the insulating material formed on at least one side of the gate structure.
18. An integrated circuit with an imaging array comprising:
at least one pixel comprising:
a photosensitive region;
a gate structure for a row select gate;
a layer of an insulating material formed over the photosensitive region; and
a spacer of the insulating material formed on at least one side of the gate structure; and
a peripheral circuit, said peripheral circuit having at least one transistor with a second gate structure and a spacer of the insulating material formed on at least one side of the second gate structure.
19. An integrated circuit with an imaging array comprising:
at least one pixel comprising:
a photosensitive region;
a gate structure;
a layer of an insulating material formed over the photosensitive region; and
a spacer of the insulating material formed on at least one side of the gate structure; and
a peripheral circuit, said peripheral circuit having at least one transistor with a second gate structure for a row select gate and a spacer of the insulating material formed on at least one side of the second gate structure.